address_a[9] => ram_block3a10.PORTAADDR9
address_a[9] => ram_block3a11.PORTAADDR9
address_a[10] => ram_block3a0.PORTAADDR10
address_a[10] => ram_block3a1.PORTAADDR10
address_a[10] => ram_block3a2.PORTAADDR10
address_a[10] => ram_block3a3.PORTAADDR10
address_a[10] => ram_block3a4.PORTAADDR10
address_a[10] => ram_block3a5.PORTAADDR10
address_a[10] => ram_block3a6.PORTAADDR10
address_a[10] => ram_block3a7.PORTAADDR10
address_a[10] => ram_block3a8.PORTAADDR10
address_a[10] => ram_block3a9.PORTAADDR10
address_a[10] => ram_block3a10.PORTAADDR10
address_a[10] => ram_block3a11.PORTAADDR10
address_a[11] => ram_block3a0.PORTAADDR11
address_a[11] => ram_block3a1.PORTAADDR11
address_a[11] => ram_block3a2.PORTAADDR11
address_a[11] => ram_block3a3.PORTAADDR11
address_a[11] => ram_block3a4.PORTAADDR11
address_a[11] => ram_block3a5.PORTAADDR11
address_a[11] => ram_block3a6.PORTAADDR11
address_a[11] => ram_block3a7.PORTAADDR11
address_a[11] => ram_block3a8.PORTAADDR11
address_a[11] => ram_block3a9.PORTAADDR11
address_a[11] => ram_block3a10.PORTAADDR11
address_a[11] => ram_block3a11.PORTAADDR11
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[0] => ram_block3a10.PORTBADDR
address_b[0] => ram_block3a11.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[1] => ram_block3a10.PORTBADDR1
address_b[1] => ram_block3a11.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[2] => ram_block3a10.PORTBADDR2
address_b[2] => ram_block3a11.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[3] => ram_block3a10.PORTBADDR3
address_b[3] => ram_block3a11.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[4] => ram_block3a10.PORTBADDR4
address_b[4] => ram_block3a11.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[5] => ram_block3a10.PORTBADDR5
address_b[5] => ram_block3a11.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[6] => ram_block3a8.PORTBADDR6
address_b[6] => ram_block3a9.PORTBADDR6
address_b[6] => ram_block3a10.PORTBADDR6
address_b[6] => ram_block3a11.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[7] => ram_block3a8.PORTBADDR7
address_b[7] => ram_block3a9.PORTBADDR7
address_b[7] => ram_block3a10.PORTBADDR7
address_b[7] => ram_block3a11.PORTBADDR7
address_b[8] => ram_block3a0.PORTBADDR8
address_b[8] => ram_block3a1.PORTBADDR8
address_b[8] => ram_block3a2.PORTBADDR8
address_b[8] => ram_block3a3.PORTBADDR8
address_b[8] => ram_block3a4.PORTBADDR8
address_b[8] => ram_block3a5.PORTBADDR8
address_b[8] => ram_block3a6.PORTBADDR8
address_b[8] => ram_block3a7.PORTBADDR8
address_b[8] => ram_block3a8.PORTBADDR8
address_b[8] => ram_block3a9.PORTBADDR8
address_b[8] => ram_block3a10.PORTBADDR8
address_b[8] => ram_block3a11.PORTBADDR8
address_b[9] => ram_block3a0.PORTBADDR9
address_b[9] => ram_block3a1.PORTBADDR9
address_b[9] => ram_block3a2.PORTBADDR9
address_b[9] => ram_block3a3.PORTBADDR9
address_b[9] => ram_block3a4.PORTBADDR9
address_b[9] => ram_block3a5.PORTBADDR9
address_b[9] => ram_block3a6.PORTBADDR9
address_b[9] => ram_block3a7.PORTBADDR9
address_b[9] => ram_block3a8.PORTBADDR9
address_b[9] => ram_block3a9.PORTBADDR9
address_b[9] => ram_block3a10.PORTBADDR9
address_b[9] => ram_block3a11.PORTBADDR9
address_b[10] => ram_block3a0.PORTBADDR10
address_b[10] => ram_block3a1.PORTBADDR10
address_b[10] => ram_block3a2.PORTBADDR10
address_b[10] => ram_block3a3.PORTBADDR10
address_b[10] => ram_block3a4.PORTBADDR10
address_b[10] => ram_block3a5.PORTBADDR10
address_b[10] => ram_block3a6.PORTBADDR10
address_b[10] => ram_block3a7.PORTBADDR10
address_b[10] => ram_block3a8.PORTBADDR10
address_b[10] => ram_block3a9.PORTBADDR10
address_b[10] => ram_block3a10.PORTBADDR10
address_b[10] => ram_block3a11.PORTBADDR10
address_b[11] => ram_block3a0.PORTBADDR11
address_b[11] => ram_block3a1.PORTBADDR11
address_b[11] => ram_block3a2.PORTBADDR11
address_b[11] => ram_block3a3.PORTBADDR11
address_b[11] => ram_block3a4.PORTBADDR11
address_b[11] => ram_block3a5.PORTBADDR11
address_b[11] => ram_block3a6.PORTBADDR11
address_b[11] => ram_block3a7.PORTBADDR11
address_b[11] => ram_block3a8.PORTBADDR11
address_b[11] => ram_block3a9.PORTBADDR11
address_b[11] => ram_block3a10.PORTBADDR11
address_b[11] => ram_block3a11.PORTBADDR11
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock0 => ram_block3a8.CLK0
clock0 => ram_block3a9.CLK0
clock0 => ram_block3a10.CLK0
clock0 => ram_block3a11.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
clock1 => ram_block3a8.CLK1
clock1 => ram_block3a9.CLK1
clock1 => ram_block3a10.CLK1
clock1 => ram_block3a11.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
data_b[8] => ram_block3a8.PORTBDATAIN
data_b[9] => ram_block3a9.PORTBDATAIN
data_b[10] => ram_block3a10.PORTBDATAIN
data_b[11] => ram_block3a11.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_a[8] <= ram_block3a8.PORTADATAOUT
q_a[9] <= ram_block3a9.PORTADATAOUT
q_a[10] <= ram_block3a10.PORTADATAOUT
q_a[11] <= ram_block3a11.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
q_b[8] <= ram_block3a8.PORTBDATAOUT
q_b[9] <= ram_block3a9.PORTBDATAOUT
q_b[10] <= ram_block3a10.PORTBDATAOUT
q_b[11] <= ram_block3a11.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE
wren_b => ram_block3a8.PORTBRE
wren_b => ram_block3a9.PORTBRE
wren_b => ram_block3a10.PORTBRE
wren_b => ram_block3a11.PORTBRE


|dds|cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= ram_rom_addr_reg[8].DB_MAX_OUTPUT_PORT_TYPE
address[9] <= ram_rom_addr_reg[9].DB_MAX_OUTPUT_PORT_TYPE
address[10] <= ram_rom_addr_reg[10].DB_MAX_OUTPUT_PORT_TYPE
address[11] <= ram_rom_addr_reg[11].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= enable_write~0.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_write[8] <= ram_rom_data_reg[8].DB_MAX_OUTPUT_PORT_TYPE
data_write[9] <= ram_rom_data_reg[9].DB_MAX_OUTPUT_PORT_TYPE
data_write[10] <= ram_rom_data_reg[10].DB_MAX_OUTPUT_PORT_TYPE
data_write[11] <= ram_rom_data_reg[11].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~23.DATAB
data_read[1] => ram_rom_data_reg~22.DATAB
data_read[2] => ram_rom_data_reg~21.DATAB
data_read[3] => ram_rom_data_reg~20.DATAB
data_read[4] => ram_rom_data_reg~19.DATAB
data_read[5] => ram_rom_data_reg~18.DATAB
data_read[6] => ram_rom_data_reg~17.DATAB
data_read[7] => ram_rom_data_reg~16.DATAB
data_read[8] => ram_rom_data_reg~15.DATAB
data_read[9] => ram_rom_data_reg~14.DATAB
data_read[10] => ram_rom_data_reg~13.DATAB
data_read[11] => ram_rom_data_reg~12.DATAB
raw_tck => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.TCK
raw_tck => is_in_use_reg.CLK
raw_tck => bypass_reg_out.CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[8].CLK
raw_tck => ram_rom_data_reg[9].CLK
raw_tck => ram_rom_data_reg[10].CLK
raw_tck => ram_rom_data_reg[11].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[8].CLK
raw_tck => ram_rom_addr_reg[9].CLK
raw_tck => ram_rom_addr_reg[1