?? adi_shift.v
字號:
`timescale 1 ps / 1ps
module ADI_Shift (
data_in,
otr8,
rxclk_p,
rxclk_n,
fco_en_p,
fco_en_n,
par_data_o,
par_data_a,
par_data_b,
par_data_c,
par_data_d,
fco_latch
);
input [3:0] data_in;
input rxclk_p, rxclk_n, fco_en_p, fco_en_n;
input otr8, fco_latch;
output [3:0] par_data_o;
output [13:0] par_data_a, par_data_b, par_data_c, par_data_d;
reg otr8_r;
reg din0a_pr, din0b_pr, din0c_pr, din0d_pr;
reg din0a_nr, din0b_nr, din0c_nr, din0d_nr;
wire [3:0] par_data_o;
wire [13:0] par_data_a, par_data_b, par_data_c, par_data_d;
wire otr8_0, otr8_1, otr8_2, otr8_3;
wire otr8_4, otr8_5, otr8_6;
wire din0a_p, din0a_n, din0b_p, din0b_n;
wire din0c_p, din0c_n, din0d_p, din0d_n;
wire din1a_p, din1a_n, din1b_p, din1b_n;
wire din1c_p, din1c_n, din1d_p, din1d_n;
wire din2a_p, din2a_n, din2b_p, din2b_n;
wire din2c_p, din2c_n, din2d_p, din2d_n;
wire din3a_p, din3a_n, din3b_p, din3b_n;
wire din3c_p, din3c_n, din3d_p, din3d_n;
wire din4a_p, din4a_n, din4b_p, din4b_n;
wire din4c_p, din4c_n, din4d_p, din4d_n;
wire din5a_p, din5a_n, din5b_p, din5b_n;
wire din5c_p, din5c_n, din5d_p, din5d_n;
wire din6a_p, din6a_n, din6b_p, din6b_n;
wire din6c_p, din6c_n, din6d_p, din6d_n;
wire dout06o, dout05o, dout04o, dout03o;
wire dout13a, dout12a;
wire dout11a, dout10a, dout09a, dout08a;
wire dout07a, dout06a, dout05a, dout04a;
wire dout03a, dout02a, dout01a, dout00a;
wire dout13b, dout12b;
wire dout11b, dout10b, dout09b, dout08b;
wire dout07b, dout06b, dout05b, dout04b;
wire dout03b, dout02b, dout01b, dout00b;
wire dout13c, dout12c;
wire dout11c, dout10c, dout09c, dout08c;
wire dout07c, dout06c, dout05c, dout04c;
wire dout03c, dout02c, dout01c, dout00c;
wire dout13d, dout12d;
wire dout11d, dout10d, dout09d, dout08d;
wire dout07d, dout06d, dout05d, dout04d;
wire dout03d, dout02d, dout01d, dout00d;
reg dout06o_x, dout05o_x, dout04o_x, dout03o_x;
reg dout13a_x, dout12a_x;
reg dout11a_x, dout10a_x, dout09a_x, dout08a_x;
reg dout07a_x, dout06a_x, dout05a_x, dout04a_x;
reg dout03a_x, dout02a_x, dout01a_x, dout00a_x;
reg dout13b_x, dout12b_x;
reg dout11b_x, dout10b_x, dout09b_x, dout08b_x;
reg dout07b_x, dout06b_x, dout05b_x, dout04b_x;
reg dout03b_x, dout02b_x, dout01b_x, dout00b_x;
reg dout13c_x, dout12c_x;
reg dout11c_x, dout10c_x, dout09c_x, dout08c_x;
reg dout07c_x, dout06c_x, dout05c_x, dout04c_x;
reg dout03c_x, dout02c_x, dout01c_x, dout00c_x;
reg dout13d_x, dout12d_x;
reg dout11d_x, dout10d_x, dout09d_x, dout08d_x;
reg dout07d_x, dout06d_x, dout05d_x, dout04d_x;
reg dout03d_x, dout02d_x, dout01d_x, dout00d_x;
// initial shift registers, positive edge
always @(posedge rxclk_p)
begin
otr8_r <= otr8;
din0a_pr <= data_in[3];
din0b_pr <= data_in[2];
din0c_pr <= data_in[1];
din0d_pr <= data_in[0];
end
// initial shift registers, negative edge
always @(posedge rxclk_n)
begin
din0a_nr <= data_in[3];
din0b_nr <= data_in[2];
din0c_nr <= data_in[1];
din0d_nr <= data_in[0];
end
// shift 7 bits deep for up to 14-bit ADC's
FD fdp0o(.C(rxclk_p), .D(otr8_r), .Q(otr8_0));
FD fdp0a(.C(rxclk_p), .D(din0a_pr), .Q(din0a_p));
FD fdp0b(.C(rxclk_p), .D(din0b_pr), .Q(din0b_p));
FD fdp0c(.C(rxclk_p), .D(din0c_pr), .Q(din0c_p));
FD fdp0d(.C(rxclk_p), .D(din0d_pr), .Q(din0d_p));
FD fdn0a(.C(rxclk_n), .D(din0a_nr), .Q(din0a_n));
FD fdn0b(.C(rxclk_n), .D(din0b_nr), .Q(din0b_n));
FD fdn0c(.C(rxclk_n), .D(din0c_nr), .Q(din0c_n));
FD fdn0d(.C(rxclk_n), .D(din0d_nr), .Q(din0d_n));
FD fdp1o(.C(rxclk_p), .D(otr8_0), .Q(otr8_1));
FD fdp1a(.C(rxclk_p), .D(din0a_p), .Q(din1a_p));
FD fdp1b(.C(rxclk_p), .D(din0b_p), .Q(din1b_p));
FD fdp1c(.C(rxclk_p), .D(din0c_p), .Q(din1c_p));
FD fdp1d(.C(rxclk_p), .D(din0d_p), .Q(din1d_p));
FD fdn1a(.C(rxclk_n), .D(din0a_n), .Q(din1a_n));
FD fdn1b(.C(rxclk_n), .D(din0b_n), .Q(din1b_n));
FD fdn1c(.C(rxclk_n), .D(din0c_n), .Q(din1c_n));
FD fdn1d(.C(rxclk_n), .D(din0d_n), .Q(din1d_n));
FD fdp2o(.C(rxclk_p), .D(otr8_1), .Q(otr8_2));
FD fdp2a(.C(rxclk_p), .D(din1a_p), .Q(din2a_p));
FD fdp2b(.C(rxclk_p), .D(din1b_p), .Q(din2b_p));
FD fdp2c(.C(rxclk_p), .D(din1c_p), .Q(din2c_p));
FD fdp2d(.C(rxclk_p), .D(din1d_p), .Q(din2d_p));
FD fdn2a(.C(rxclk_n), .D(din1a_n), .Q(din2a_n));
FD fdn2b(.C(rxclk_n), .D(din1b_n), .Q(din2b_n));
FD fdn2c(.C(rxclk_n), .D(din1c_n), .Q(din2c_n));
FD fdn2d(.C(rxclk_n), .D(din1d_n), .Q(din2d_n));
FD fdp3o(.C(rxclk_p), .D(otr8_2), .Q(otr8_3));
FD fdp3a(.C(rxclk_p), .D(din2a_p), .Q(din3a_p));
FD fdp3b(.C(rxclk_p), .D(din2b_p), .Q(din3b_p));
FD fdp3c(.C(rxclk_p), .D(din2c_p), .Q(din3c_p));
FD fdp3d(.C(rxclk_p), .D(din2d_p), .Q(din3d_p));
FD fdn3a(.C(rxclk_n), .D(din2a_n), .Q(din3a_n));
FD fdn3b(.C(rxclk_n), .D(din2b_n), .Q(din3b_n));
FD fdn3c(.C(rxclk_n), .D(din2c_n), .Q(din3c_n));
FD fdn3d(.C(rxclk_n), .D(din2d_n), .Q(din3d_n));
FD fdp4o(.C(rxclk_p), .D(otr8_3), .Q(otr8_4));
FD fdp4a(.C(rxclk_p), .D(din3a_p), .Q(din4a_p));
FD fdp4b(.C(rxclk_p), .D(din3b_p), .Q(din4b_p));
FD fdp4c(.C(rxclk_p), .D(din3c_p), .Q(din4c_p));
FD fdp4d(.C(rxclk_p), .D(din3d_p), .Q(din4d_p));
FD fdn4a(.C(rxclk_n), .D(din3a_n), .Q(din4a_n));
FD fdn4b(.C(rxclk_n), .D(din3b_n), .Q(din4b_n));
FD fdn4c(.C(rxclk_n), .D(din3c_n), .Q(din4c_n));
FD fdn4d(.C(rxclk_n), .D(din3d_n), .Q(din4d_n));
FD fdp5o(.C(rxclk_p), .D(otr8_4), .Q(otr8_5));
FD fdp5a(.C(rxclk_p), .D(din4a_p), .Q(din5a_p));
FD fdp5b(.C(rxclk_p), .D(din4b_p), .Q(din5b_p));
FD fdp5c(.C(rxclk_p), .D(din4c_p), .Q(din5c_p));
FD fdp5d(.C(rxclk_p), .D(din4d_p), .Q(din5d_p));
FD fdn5a(.C(rxclk_n), .D(din4a_n), .Q(din5a_n));
FD fdn5b(.C(rxclk_n), .D(din4b_n), .Q(din5b_n));
FD fdn5c(.C(rxclk_n), .D(din4c_n), .Q(din5c_n));
FD fdn5d(.C(rxclk_n), .D(din4d_n), .Q(din5d_n));
FD fdp6o(.C(rxclk_p), .D(otr8_5), .Q(otr8_6));
FD fdp6a(.C(rxclk_p), .D(din5a_p), .Q(din6a_p));
FD fdp6b(.C(rxclk_p), .D(din5b_p), .Q(din6b_p));
FD fdp6c(.C(rxclk_p), .D(din5c_p), .Q(din6c_p));
FD fdp6d(.C(rxclk_p), .D(din5d_p), .Q(din6d_p));
FD fdn6a(.C(rxclk_n), .D(din5a_n), .Q(din6a_n));
FD fdn6b(.C(rxclk_n), .D(din5b_n), .Q(din6b_n));
FD fdn6c(.C(rxclk_n), .D(din5c_n), .Q(din6c_n));
FD fdn6d(.C(rxclk_n), .D(din5d_n), .Q(din6d_n));
// latch parallel data for OTR channel (AD9289 only)
FDCE fd06o(.CE(fco_en_p), .C(rxclk_p), .D(otr8_6), .Q(dout06o), .CLR(1'b0));
FDCE fd05o(.CE(fco_en_p), .C(rxclk_p), .D(otr8_5), .Q(dout05o), .CLR(1'b0));
FDCE fd04o(.CE(fco_en_p), .C(rxclk_p), .D(otr8_4), .Q(dout04o), .CLR(1'b0));
FDCE fd03o(.CE(fco_en_p), .C(rxclk_p), .D(otr8_3), .Q(dout03o), .CLR(1'b0));
// latch parallel data for channel A
FDCE fd13a(.CE(fco_en_p), .C(rxclk_p), .D(din6a_p), .Q(dout13a), .CLR(1'b0));
FDCE fd12a(.CE(fco_en_n), .C(rxclk_n), .D(din6a_n), .Q(dout12a), .CLR(1'b0));
FDCE fd11a(.CE(fco_en_p), .C(rxclk_p), .D(din5a_p), .Q(dout11a), .CLR(1'b0));
FDCE fd10a(.CE(fco_en_n), .C(rxclk_n), .D(din5a_n), .Q(dout10a), .CLR(1'b0));
FDCE fd09a(.CE(fco_en_p), .C(rxclk_p), .D(din4a_p), .Q(dout09a), .CLR(1'b0));
FDCE fd08a(.CE(fco_en_n), .C(rxclk_n), .D(din4a_n), .Q(dout08a), .CLR(1'b0));
FDCE fd07a(.CE(fco_en_p), .C(rxclk_p), .D(din3a_p), .Q(dout07a), .CLR(1'b0));
FDCE fd06a(.CE(fco_en_n), .C(rxclk_n), .D(din3a_n), .Q(dout06a), .CLR(1'b0));
FDCE fd05a(.CE(fco_en_p), .C(rxclk_p), .D(din2a_p), .Q(dout05a), .CLR(1'b0));
FDCE fd04a(.CE(fco_en_n), .C(rxclk_n), .D(din2a_n), .Q(dout04a), .CLR(1'b0));
FDCE fd03a(.CE(fco_en_p), .C(rxclk_p), .D(din1a_p), .Q(dout03a), .CLR(1'b0));
FDCE fd02a(.CE(fco_en_n), .C(rxclk_n), .D(din1a_n), .Q(dout02a), .CLR(1'b0));
FDCE fd01a(.CE(fco_en_p), .C(rxclk_p), .D(din0a_p), .Q(dout01a), .CLR(1'b0));
FDCE fd00a(.CE(fco_en_n), .C(rxclk_n), .D(din0a_n), .Q(dout00a), .CLR(1'b0));
// latch parallel data for channel B
FDCE fd13b(.CE(fco_en_p), .C(rxclk_p), .D(din6b_p), .Q(dout13b), .CLR(1'b0));
FDCE fd12b(.CE(fco_en_n), .C(rxclk_n), .D(din6b_n), .Q(dout12b), .CLR(1'b0));
FDCE fd11b(.CE(fco_en_p), .C(rxclk_p), .D(din5b_p), .Q(dout11b), .CLR(1'b0));
FDCE fd10b(.CE(fco_en_n), .C(rxclk_n), .D(din5b_n), .Q(dout10b), .CLR(1'b0));
FDCE fd09b(.CE(fco_en_p), .C(rxclk_p), .D(din4b_p), .Q(dout09b), .CLR(1'b0));
FDCE fd08b(.CE(fco_en_n), .C(rxclk_n), .D(din4b_n), .Q(dout08b), .CLR(1'b0));
FDCE fd07b(.CE(fco_en_p), .C(rxclk_p), .D(din3b_p), .Q(dout07b), .CLR(1'b0));
FDCE fd06b(.CE(fco_en_n), .C(rxclk_n), .D(din3b_n), .Q(dout06b), .CLR(1'b0));
FDCE fd05b(.CE(fco_en_p), .C(rxclk_p), .D(din2b_p), .Q(dout05b), .CLR(1'b0));
FDCE fd04b(.CE(fco_en_n), .C(rxclk_n), .D(din2b_n), .Q(dout04b), .CLR(1'b0));
FDCE fd03b(.CE(fco_en_p), .C(rxclk_p), .D(din1b_p), .Q(dout03b), .CLR(1'b0));
FDCE fd02b(.CE(fco_en_n), .C(rxclk_n), .D(din1b_n), .Q(dout02b), .CLR(1'b0));
FDCE fd01b(.CE(fco_en_p), .C(rxclk_p), .D(din0b_p), .Q(dout01b), .CLR(1'b0));
FDCE fd00b(.CE(fco_en_n), .C(rxclk_n), .D(din0b_n), .Q(dout00b), .CLR(1'b0));
// latch parallel data for channel C
FDCE fd13c(.CE(fco_en_p), .C(rxclk_p), .D(din6c_p), .Q(dout13c), .CLR(1'b0));
FDCE fd12c(.CE(fco_en_n), .C(rxclk_n), .D(din6c_n), .Q(dout12c), .CLR(1'b0));
FDCE fd11c(.CE(fco_en_p), .C(rxclk_p), .D(din5c_p), .Q(dout11c), .CLR(1'b0));
FDCE fd10c(.CE(fco_en_n), .C(rxclk_n), .D(din5c_n), .Q(dout10c), .CLR(1'b0));
FDCE fd09c(.CE(fco_en_p), .C(rxclk_p), .D(din4c_p), .Q(dout09c), .CLR(1'b0));
FDCE fd08c(.CE(fco_en_n), .C(rxclk_n), .D(din4c_n), .Q(dout08c), .CLR(1'b0));
FDCE fd07c(.CE(fco_en_p), .C(rxclk_p), .D(din3c_p), .Q(dout07c), .CLR(1'b0));
FDCE fd06c(.CE(fco_en_n), .C(rxclk_n), .D(din3c_n), .Q(dout06c), .CLR(1'b0));
FDCE fd05c(.CE(fco_en_p), .C(rxclk_p), .D(din2c_p), .Q(dout05c), .CLR(1'b0));
FDCE fd04c(.CE(fco_en_n), .C(rxclk_n), .D(din2c_n), .Q(dout04c), .CLR(1'b0));
FDCE fd03c(.CE(fco_en_p), .C(rxclk_p), .D(din1c_p), .Q(dout03c), .CLR(1'b0));
FDCE fd02c(.CE(fco_en_n), .C(rxclk_n), .D(din1c_n), .Q(dout02c), .CLR(1'b0));
FDCE fd01c(.CE(fco_en_p), .C(rxclk_p), .D(din0c_p), .Q(dout01c), .CLR(1'b0));
FDCE fd00c(.CE(fco_en_n), .C(rxclk_n), .D(din0c_n), .Q(dout00c), .CLR(1'b0));
// latch parallel data for channel D
FDCE fd13d(.CE(fco_en_p), .C(rxclk_p), .D(din6d_p), .Q(dout13d), .CLR(1'b0));
FDCE fd12d(.CE(fco_en_n), .C(rxclk_n), .D(din6d_n), .Q(dout12d), .CLR(1'b0));
FDCE fd11d(.CE(fco_en_p), .C(rxclk_p), .D(din5d_p), .Q(dout11d), .CLR(1'b0));
FDCE fd10d(.CE(fco_en_n), .C(rxclk_n), .D(din5d_n), .Q(dout10d), .CLR(1'b0));
FDCE fd09d(.CE(fco_en_p), .C(rxclk_p), .D(din4d_p), .Q(dout09d), .CLR(1'b0));
FDCE fd08d(.CE(fco_en_n), .C(rxclk_n), .D(din4d_n), .Q(dout08d), .CLR(1'b0));
FDCE fd07d(.CE(fco_en_p), .C(rxclk_p), .D(din3d_p), .Q(dout07d), .CLR(1'b0));
FDCE fd06d(.CE(fco_en_n), .C(rxclk_n), .D(din3d_n), .Q(dout06d), .CLR(1'b0));
FDCE fd05d(.CE(fco_en_p), .C(rxclk_p), .D(din2d_p), .Q(dout05d), .CLR(1'b0));
FDCE fd04d(.CE(fco_en_n), .C(rxclk_n), .D(din2d_n), .Q(dout04d), .CLR(1'b0));
FDCE fd03d(.CE(fco_en_p), .C(rxclk_p), .D(din1d_p), .Q(dout03d), .CLR(1'b0));
FDCE fd02d(.CE(fco_en_n), .C(rxclk_n), .D(din1d_n), .Q(dout02d), .CLR(1'b0));
FDCE fd01d(.CE(fco_en_p), .C(rxclk_p), .D(din0d_p), .Q(dout01d), .CLR(1'b0));
FDCE fd00d(.CE(fco_en_n), .C(rxclk_n), .D(din0d_n), .Q(dout00d), .CLR(1'b0));
// transition from high speed clock domain to low speed clock
always @(posedge rxclk_p)
if(fco_latch) begin
dout06o_x <= dout06o; dout05o_x <= dout05o;
dout04o_x <= dout04o; dout03o_x <= dout03o;
dout13a_x <= dout13a; dout12a_x <= dout12a;
dout11a_x <= dout11a; dout10a_x <= dout10a; dout09a_x <= dout09a;
dout08a_x <= dout08a; dout07a_x <= dout07a; dout06a_x <= dout06a;
dout05a_x <= dout05a; dout04a_x <= dout04a; dout03a_x <= dout03a;
dout02a_x <= dout02a; dout01a_x <= dout01a; dout00a_x <= dout00a;
dout13b_x <= dout13b; dout12b_x <= dout12b;
dout11b_x <= dout11b; dout10b_x <= dout10b; dout09b_x <= dout09b;
dout08b_x <= dout08b; dout07b_x <= dout07b; dout06b_x <= dout06b;
dout05b_x <= dout05b; dout04b_x <= dout04b; dout03b_x <= dout03b;
dout02b_x <= dout02b; dout01b_x <= dout01b; dout00b_x <= dout00b;
dout13c_x <= dout13c; dout12c_x <= dout12c;
dout11c_x <= dout11c; dout10c_x <= dout10c; dout09c_x <= dout09c;
dout08c_x <= dout08c; dout07c_x <= dout07c; dout06c_x <= dout06c;
dout05c_x <= dout05c; dout04c_x <= dout04c; dout03c_x <= dout03c;
dout02c_x <= dout02c; dout01c_x <= dout01c; dout00c_x <= dout00c;
dout13d_x <= dout13d; dout12d_x <= dout12d;
dout11d_x <= dout11d; dout10d_x <= dout10d; dout09d_x <= dout09d;
dout08d_x <= dout08d; dout07d_x <= dout07d; dout06d_x <= dout06d;
dout05d_x <= dout05d; dout04d_x <= dout04d; dout03d_x <= dout03d;
dout02d_x <= dout02d; dout01d_x <= dout01d; dout00d_x <= dout00d;
end
assign par_data_o = {dout06o_x, dout05o_x, dout04o_x, dout03o_x};
assign par_data_a = {dout13a_x, dout12a_x, dout11a_x, dout10a_x, dout09a_x, dout08a_x, dout07a_x, dout06a_x, dout05a_x, dout04a_x, dout03a_x, dout02a_x, dout01a_x, dout00a_x};
assign par_data_b = {dout13b_x, dout12b_x, dout11b_x, dout10b_x, dout09b_x, dout08b_x, dout07b_x, dout06b_x, dout05b_x, dout04b_x, dout03b_x, dout02b_x, dout01b_x, dout00b_x};
assign par_data_c = {dout13c_x, dout12c_x, dout11c_x, dout10c_x, dout09c_x, dout08c_x, dout07c_x, dout06c_x, dout05c_x, dout04c_x, dout03c_x, dout02c_x, dout01c_x, dout00c_x};
assign par_data_d = {dout13d_x, dout12d_x, dout11d_x, dout10d_x, dout09d_x, dout08d_x, dout07d_x, dout06d_x, dout05d_x, dout04d_x, dout03d_x, dout02d_x, dout01d_x, dout00d_x};
endmodule
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