module ADI_Top(
	 rst,
	 clk_ab,
	 clk_cd,
	 dco_n,
	 dco_p,
	 fco_n,
	 fco_p,
	 otr_p,
	 otr_n,
	 din_a_n,
	 din_a_p,
	 din_b_n,
	 din_b_p,
	 din_c_n,
	 din_c_p,
	 din_d_n,
	 din_d_p,
	 out_data_ab,
	 out_data_cd,
	 sel_ab,
	 sel_cd,
	 res_sel_0,
	 res_sel_1,
	 mode_sel
	 );

input rst, dco_n, dco_p, fco_n, fco_p;
input din_a_n, din_a_p, din_b_n, din_b_p;
input din_c_n, din_c_p, din_d_n, din_d_p;
input sel_ab, sel_cd, res_sel_0, res_sel_1;
input mode_sel, otr_p, otr_n;

output clk_ab, clk_cd;
output [13:0] out_data_ab, out_data_cd;

wire fco_clk, dco, frame_in, otr8;
wire data_a, data_b, data_c, data_d;
wire [1:0] par_data_abo, par_data_cdo;
wire [3:0] data_in, data_out_o;
wire [13:0] data_out_a, data_out_b, data_out_c, data_out_d;
wire [13:0] par_data_ab, par_data_cd;

assign data_in = {data_a, data_b, data_c, data_d};

// LVDS Input Buffers
IBUFGDS_LVDS_33 lvds_dco_ibufg(.I(dco_p), .IB(dco_n), .O(dco));
IBUFGDS_LVDS_33 lvds_frame_ibufg(.I(fco_p), .IB(fco_n), .O(frame_in));
IBUFDS_LVDS_33 lvds_data_ibufo(.I(otr_p), .IB(otr_n), .O(otr8));	
IBUFDS_LVDS_33 lvds_data_ibufa(.I(din_a_p), .IB(din_a_n), .O(data_a));	
IBUFDS_LVDS_33 lvds_data_ibufb(.I(din_b_p), .IB(din_b_n), .O(data_b));	
IBUFDS_LVDS_33 lvds_data_ibufc(.I(din_c_p), .IB(din_c_n), .O(data_c));	
IBUFDS_LVDS_33 lvds_data_ibufd(.I(din_d_p), .IB(din_d_n), .O(data_d));	

// set-up clocks
ADI_Clocking ADI_Clocking_inst (
	.rstin(rst),		// reset pushbutton
	.mode_sel(mode_sel),
	.res_sel_0(res_sel_0),
	.res_sel_1(res_sel_1),
	.rxclkin(dco),
	.otr8(otr8),
	.data_in(data_in),
	.frame_in(frame_in),
	.data_out_o(data_out_o),
	.data_out_a(data_out_a),
	.data_out_b(data_out_b),
	.data_out_c(data_out_c),
	.data_out_d(data_out_d),
	.fco_clk(fco_clk),
	.rxclk(rxclk));

reg [3:0] data_out_mux_o;
reg [13:0] data_out_mux_a, data_out_mux_b, data_out_mux_c, data_out_mux_d;

always @(posedge rxclk) 
  if (!fco_clk) begin
    data_out_mux_o <= data_out_o;
    data_out_mux_a <= data_out_a;
    data_out_mux_b <= data_out_b;
    data_out_mux_c <= data_out_c;
    data_out_mux_d <= data_out_d;
  end // users can access data_out_mux_a/b/c/d registers here

// FIFO board only has 2 channels, select a/b or c/d
MUXF5 muxf5_ab13 (.O(par_data_ab[13]), .I0(data_out_mux_a[13]), .I1(data_out_mux_b[13]), .S(sel_ab));
MUXF5 muxf5_ab12 (.O(par_data_ab[12]), .I0(data_out_mux_a[12]), .I1(data_out_mux_b[12]), .S(sel_ab));
MUXF5 muxf5_ab11 (.O(par_data_ab[11]), .I0(data_out_mux_a[11]), .I1(data_out_mux_b[11]), .S(sel_ab));
MUXF5 muxf5_ab10 (.O(par_data_ab[10]), .I0(data_out_mux_a[10]), .I1(data_out_mux_b[10]), .S(sel_ab));
MUXF5 muxf5_ab09 (.O(par_data_ab[09]), .I0(data_out_mux_a[09]), .I1(data_out_mux_b[09]), .S(sel_ab));
MUXF5 muxf5_ab08 (.O(par_data_ab[08]), .I0(data_out_mux_a[08]), .I1(data_out_mux_b[08]), .S(sel_ab));
MUXF5 muxf5_ab07 (.O(par_data_ab[07]), .I0(data_out_mux_a[07]), .I1(data_out_mux_b[07]), .S(sel_ab));
MUXF5 muxf5_ab06 (.O(par_data_ab[06]), .I0(data_out_mux_a[06]), .I1(data_out_mux_b[06]), .S(sel_ab));
MUXF5 muxf5_ab05 (.O(par_data_ab[05]), .I0(data_out_mux_a[05]), .I1(data_out_mux_b[05]), .S(sel_ab));
MUXF5 muxf5_ab04 (.O(par_data_ab[04]), .I0(data_out_mux_a[04]), .I1(data_out_mux_b[04]), .S(sel_ab));
MUXF5 muxf5_ab03 (.O(par_data_ab[03]), .I0(data_out_mux_a[03]), .I1(data_out_mux_b[03]), .S(sel_ab));
MUXF5 muxf5_ab02 (.O(par_data_ab[02]), .I0(data_out_mux_a[02]), .I1(data_out_mux_b[02]), .S(sel_ab));
MUXF5 muxf5_ab01 (.O(par_data_ab[01]), .I0(data_out_mux_a[01]), .I1(data_out_mux_b[01]), .S(sel_ab));
MUXF5 muxf5_ab00 (.O(par_data_ab[00]), .I0(data_out_mux_a[00]), .I1(data_out_mux_b[00]), .S(sel_ab));

MUXF5 muxf5_cd13 (.O(par_data_cd[13]), .I0(data_out_mux_c[13]), .I1(data_out_mux_d[13]), .S(sel_cd));
MUXF5 muxf5_cd12 (.O(par_data_cd[12]), .I0(data_out_mux_c[12]), .I1(data_out_mux_d[12]), .S(sel_cd));
MUXF5 muxf5_cd11 (.O(par_data_cd[11]), .I0(data_out_mux_c[11]), .I1(data_out_mux_d[11]), .S(sel_cd));
MUXF5 muxf5_cd10 (.O(par_data_cd[10]), .I0(data_out_mux_c[10]), .I1(data_out_mux_d[10]), .S(sel_cd));
MUXF5 muxf5_cd09 (.O(par_data_cd[09]), .I0(data_out_mux_c[09]), .I1(data_out_mux_d[09]), .S(sel_cd));
MUXF5 muxf5_cd08 (.O(par_data_cd[08]), .I0(data_out_mux_c[08]), .I1(data_out_mux_d[08]), .S(sel_cd));
MUXF5 muxf5_cd07 (.O(par_data_cd[07]), .I0(data_out_mux_c[07]), .I1(data_out_mux_d[07]), .S(sel_cd));
MUXF5 muxf5_cd06 (.O(par_data_cd[06]), .I0(data_out_mux_c[06]), .I1(data_out_mux_d[06]), .S(sel_cd));
MUXF5 muxf5_cd05 (.O(par_data_cd[05]), .I0(data_out_mux_c[05]), .I1(data_out_mux_d[05]), .S(sel_cd));
MUXF5 muxf5_cd04 (.O(par_data_cd[04]), .I0(data_out_mux_c[04]), .I1(data_out_mux_d[04]), .S(sel_cd));
MUXF5 muxf5_cd03 (.O(par_data_cd[03]), .I0(data_out_mux_c[03]), .I1(data_out_mux_d[03]), .S(sel_cd));
MUXF5 muxf5_cd02 (.O(par_data_cd[02]), .I0(data_out_mux_c[02]), .I1(data_out_mux_d[02]), .S(sel_cd));
MUXF5 muxf5_cd01 (.O(par_data_cd[01]), .I0(data_out_mux_c[01]), .I1(data_out_mux_d[01]), .S(sel_cd));
MUXF5 muxf5_cd00 (.O(par_data_cd[00]), .I0(data_out_mux_c[00]), .I1(data_out_mux_d[00]), .S(sel_cd));

reg fco_del_a, fco_del_b, fco_del;

// line up final output clock
always @(posedge rxclk) begin
  fco_del_a <= fco_clk;
  fco_del_b <= fco_del_a;
  fco_del <= !fco_del_b;
  end

reg [2:0] clr_cntrl;

// select ADC resolution
always @(posedge rxclk)
	case({res_sel_1, res_sel_0})
		2'b11 : clr_cntrl <= 3'b000; // 14 bits
		2'b10 : clr_cntrl <= 3'b001; // 12 bits
		2'b01 : clr_cntrl <= 3'b011; // 10 bits
		2'b00 : clr_cntrl <= 3'b111; //  8 bits
	endcase

// select OTR data if using 8-bit ADC (AD9289)
MUXF5 muxf5_cdoa (.O(par_data_abo[1]), .I0(par_data_ab[05]), .I1(data_out_mux_o[3]), .S(clr_cntrl[2]));
MUXF5 muxf5_cdob (.O(par_data_abo[0]), .I0(par_data_ab[04]), .I1(data_out_mux_o[2]), .S(clr_cntrl[2]));
MUXF5 muxf5_cdoc (.O(par_data_cdo[1]), .I0(par_data_cd[05]), .I1(data_out_mux_o[1]), .S(clr_cntrl[2]));
MUXF5 muxf5_cdod (.O(par_data_cdo[0]), .I0(par_data_cd[04]), .I1(data_out_mux_o[0]), .S(clr_cntrl[2]));

// final data outputs
FDCE fd_out_ab13(.CE(fco_del), .C(rxclk), .D(par_data_ab[13]), .Q(out_data_ab[13]), .CLR(1'b0));
FDCE fd_out_ab12(.CE(fco_del), .C(rxclk), .D(par_data_ab[12]), .Q(out_data_ab[12]), .CLR(1'b0));
FDCE fd_out_ab11(.CE(fco_del), .C(rxclk), .D(par_data_ab[11]), .Q(out_data_ab[11]), .CLR(1'b0));
FDCE fd_out_ab10(.CE(fco_del), .C(rxclk), .D(par_data_ab[10]), .Q(out_data_ab[10]), .CLR(1'b0));
FDCE fd_out_ab09(.CE(fco_del), .C(rxclk), .D(par_data_ab[09]), .Q(out_data_ab[09]), .CLR(1'b0));
FDCE fd_out_ab08(.CE(fco_del), .C(rxclk), .D(par_data_ab[08]), .Q(out_data_ab[08]), .CLR(1'b0));
FDCE fd_out_ab07(.CE(fco_del), .C(rxclk), .D(par_data_ab[07]), .Q(out_data_ab[07]), .CLR(1'b0));
FDCE fd_out_ab06(.CE(fco_del), .C(rxclk), .D(par_data_ab[06]), .Q(out_data_ab[06]), .CLR(1'b0));
FDCE fd_out_ab05(.CE(fco_del), .C(rxclk), .D(par_data_abo[1]), .Q(out_data_ab[05]), .CLR(1'b0));
FDCE fd_out_ab04(.CE(fco_del), .C(rxclk), .D(par_data_abo[0]), .Q(out_data_ab[04]), .CLR(1'b0));
FDCE fd_out_ab03(.CE(fco_del), .C(rxclk), .D(par_data_ab[03]), .Q(out_data_ab[03]), .CLR(clr_cntrl[1]));
FDCE fd_out_ab02(.CE(fco_del), .C(rxclk), .D(par_data_ab[02]), .Q(out_data_ab[02]), .CLR(clr_cntrl[1]));
FDCE fd_out_ab01(.CE(fco_del), .C(rxclk), .D(par_data_ab[01]), .Q(out_data_ab[01]), .CLR(clr_cntrl[0]));
FDCE fd_out_ab00(.CE(fco_del), .C(rxclk), .D(par_data_ab[00]), .Q(out_data_ab[00]), .CLR(clr_cntrl[0]));

FDCE fd_out_cd13(.CE(fco_del), .C(rxclk), .D(par_data_cd[13]), .Q(out_data_cd[13]), .CLR(1'b0));
FDCE fd_out_cd12(.CE(fco_del), .C(rxclk), .D(par_data_cd[12]), .Q(out_data_cd[12]), .CLR(1'b0));
FDCE fd_out_cd11(.CE(fco_del), .C(rxclk), .D(par_data_cd[11]), .Q(out_data_cd[11]), .CLR(1'b0));
FDCE fd_out_cd10(.CE(fco_del), .C(rxclk), .D(par_data_cd[10]), .Q(out_data_cd[10]), .CLR(1'b0));
FDCE fd_out_cd09(.CE(fco_del), .C(rxclk), .D(par_data_cd[09]), .Q(out_data_cd[09]), .CLR(1'b0));
FDCE fd_out_cd08(.CE(fco_del), .C(rxclk), .D(par_data_cd[08]), .Q(out_data_cd[08]), .CLR(1'b0));
FDCE fd_out_cd07(.CE(fco_del), .C(rxclk), .D(par_data_cd[07]), .Q(out_data_cd[07]), .CLR(1'b0));
FDCE fd_out_cd06(.CE(fco_del), .C(rxclk), .D(par_data_cd[06]), .Q(out_data_cd[06]), .CLR(1'b0));
FDCE fd_out_cd05(.CE(fco_del), .C(rxclk), .D(par_data_cdo[1]), .Q(out_data_cd[05]), .CLR(1'b0));
FDCE fd_out_cd04(.CE(fco_del), .C(rxclk), .D(par_data_cdo[0]), .Q(out_data_cd[04]), .CLR(1'b0));
FDCE fd_out_cd03(.CE(fco_del), .C(rxclk), .D(par_data_cd[03]), .Q(out_data_cd[03]), .CLR(clr_cntrl[1]));
FDCE fd_out_cd02(.CE(fco_del), .C(rxclk), .D(par_data_cd[02]), .Q(out_data_cd[02]), .CLR(clr_cntrl[1]));
FDCE fd_out_cd01(.CE(fco_del), .C(rxclk), .D(par_data_cd[01]), .Q(out_data_cd[01]), .CLR(clr_cntrl[0]));
FDCE fd_out_cd00(.CE(fco_del), .C(rxclk), .D(par_data_cd[00]), .Q(out_data_cd[00]), .CLR(clr_cntrl[0]));

// final clock outputs
FD fd_clk_ab(.C(rxclk), .D(fco_del), .Q(clk_ab));
FD fd_clk_cd(.C(rxclk), .D(fco_del), .Q(clk_cd));

endmodule