// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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//                     Lattice Semiconductor Corporation
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// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 1/24/98   :| Initial Creation
// --------------------------------------------------------------------
//
//	Module  glue.v
/*
   This module contains  the miscellaneous glue logic required for
   the PCI Target reference design.
*/
//
module glue ( pci_clk,
              pci_rst_l,
	      pci_ad_en,
	      pci_ad,
	      pci_addr,
	      pci_cbe_l,
	      pci_idsel,
	      cbe_reg_l,
	      idsel_reg
	     );

input pci_clk, pci_rst_l, pci_ad_en;
input [31:0] pci_ad;
input [3:0] pci_cbe_l;
input pci_idsel;

output [31:0] pci_addr;
output idsel_reg;
output cbe_reg_l;

reg [31:0] pci_addr;
reg [3:0] cbe_reg_l;
reg idsel_reg;
   
  
// The following registers are clock enabled
// depending on what phase the PCI transaction
// is in. They are not input registers.
always @ (posedge pci_clk or negedge pci_rst_l)
  begin 
    if (pci_rst_l == 1'b0) begin 
      pci_addr <= #1 32'b0; // reset regs
      cbe_reg_l <= #1 4'b0;
      idsel_reg <= #1 1'b0;
    end
    else if (pci_ad_en == 1'b1) begin 
      pci_addr <= #1 pci_ad; // register address
      cbe_reg_l <= #1 pci_cbe_l;
      idsel_reg <= #1 pci_idsel;
    end
    else begin 
      pci_addr <= #1 pci_addr;
      cbe_reg_l <= #1 cbe_reg_l;
      idsel_reg <= #1 idsel_reg;
    end  
  end

 
endmodule //of glue