// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 12/11/98  :| Initial Creation
// --------------------------------------------------------------------
//
//	Module  pargen
/*
   This file is the parity generator block for the 32 bit PCI Target
   reference design. It generates even parity from the pci_cbe and
   pci_dat_out signals.  Notice how the parity logic is pipelined
   to meet the critical 11ns Tco timing for pci_par. 

*/
//

module pargen (par_out, pci_cbe_l, pci_dat_out, pci_clk, par_oe);
  output par_out;
  input [3:0] pci_cbe_l;
  input [31:0] pci_dat_out;
  input pci_clk;
  input par_oe;
  
 reg cbe_reg;
 reg par3, par2, par1, par0;
 reg par_reg;
 
// Not ALL synthesis tools create an optimal parity circuit, 
// so an SOP (Sum Of Products) equivalent of the following 
// assignment is used.
// assign #2 par_out = ^{par3,par2,par1,par0,cbe_reg}; // 2^5-1=16PT's so 1 Tpd


// Special Parity block that works with all synthesis tools

 assign #2 par_out = par_reg;
 
 always @ (par3 or par2 or par1 or par0 or cbe_reg)
   begin 
     case ({par3, par2, par1, par0, cbe_reg})
       5'b00001: par_reg =  1;
       5'b00010: par_reg =  1;
       5'b00100: par_reg =  1;
       5'b00111: par_reg =  1;
       5'b01000: par_reg =  1;
       5'b01011: par_reg =  1;
       5'b01101: par_reg =  1;
       5'b01110: par_reg =  1;
       5'b10000: par_reg =  1;
       5'b10011: par_reg =  1;
       5'b10101: par_reg =  1;
       5'b10110: par_reg =  1;
       5'b11001: par_reg =  1;
       5'b11010: par_reg =  1;
       5'b11100: par_reg =  1;
       5'b11111: par_reg =  1;
       default: par_reg =  0;
     endcase
    
   end

 always @ (posedge pci_clk)
   begin 
    if (par_oe == 1'b1) begin 
     par3 <= #1 ^pci_dat_out[31:24]; // 2 Tpdi's
     par2 <= #1 ^pci_dat_out[23:16];
     par1 <= #1 ^pci_dat_out[15:8];
     par0 <= #1 ^pci_dat_out[7:0];
     cbe_reg <= #1 ^pci_cbe_l[3:0];
    end
   end
 
endmodule //of pargen