`define ADDR_8M     28'hFF80_000
`define ADDR_4M     28'hFFC0_000
`define ADDR_2M     28'hFFE0_000
`define ADDR_1M     28'hFFF0_000
`define ADDR_512K   28'hFFF8_000
`define ADDR_256K   28'hFFFC_000
`define ADDR_128K   28'hFFFE_000
`define ADDR_64K    28'hFFFF_000
`define ADDR_32K    28'hFFFF_800
`define ADDR_16K    28'hFFFF_C00
`define ADDR_8K     28'hFFFF_E00
`define ADDR_4K     28'hFFFF_F00
`define ADDR_2K     28'hFFFF_F80
`define ADDR_1K     28'hFFFF_FC0
`define ADDR_512    28'hFFFF_FE0
`define ADDR_256    28'hFFFF_FF0
`define ADDR_128    28'hFFFF_FF8
`define ADDR_64     28'hFFFF_FFC
`define ADDR_32     28'hFFFF_FFE
`define ADDR_16     28'hFFFF_FFF

/******************************************************************/
/************  End Base Address Defines Section   ***************/
/******************************************************************/



/******************************************************************/
/************    Start Reg 10h Section           ***************/
/******************************************************************/
// reg 10h (Base Address 0) BA0 Using `defines from above
parameter [31:0] BA0 = {`ADDR_1M,`PREFETCH_OFF,`ANYWHERE_IN_32,`IO_ON};
assign ba0_size = BA0[31:4]; // Used to decode hit_ba0_l
/******************************************************************/
/************    End Reg 10h Section              *****************/
/******************************************************************/



/******************************************************************/
/************    Start Reg 14h Section             ***************/
/******************************************************************/
// reg 14h (Base Address 1) BA1 Using `defines from above
parameter [31:0] BA1 = {`ADDR_1M,`PREFETCH_OFF,`ANYWHERE_IN_32,`MEM_ON};
assign ba1_size = BA1[31:4]; // Used to decode hit_ba1_l
/******************************************************************/
/************    End Reg 14h Section              *****************/
/******************************************************************/


/******************************************************************/
/************    Start Reg 2C Section               ***************/
/******************************************************************/
// reg 2Ch (SubsystemID/Subsystem VendorID)
parameter	SUB_SYSTEM_ID = 16'h0120; // User Defined Could be anything
parameter	SUB_VENDOR_ID = 16'h1022; // Set to AMD
/******************************************************************/
/************    End Reg 2Ch Section              *****************/
/******************************************************************/



/******************************************************************/
/************    Start Reg 3C Section               ***************/
/******************************************************************/
// reg 3C (Max_Lat/Min_Gnt/Interrupt Pin/ Interupt Line)
// Interupt Pin is set to 1 corresponding to inta_l

parameter INT_PIN = 8'h01;

// The int_line reg is defined here
// The software will write to this register
// to set the system IRQ used for the interrupt
always @ (posedge pci_clk or negedge pci_rst_l)
  if (pci_rst_l == 1'b0) begin 
    int_line = 8'h00;
  end 
  else if (int_line_en && !pci_cbe_l[0] ) begin // check byte enables
    int_line = pci_dat[7:0];
  end
  else begin 
    int_line = int_line;    
  end
// Max_Lat & Min_Gnt are not implemented so they are 0's in Mux
/******************************************************************/
/************    End Reg 3Ch Section              *****************/
/******************************************************************/

/******************************************************************/
/************    Start Write Enable section         ***************/
/******************************************************************/

`define write_04 (pci_addr[7:0] == 8'h04)
`define write_10 (pci_addr[7:0] == 8'h10)
`define write_14 (pci_addr[7:0] == 8'h14)
`define write_3C (pci_addr[7:0] == 8'h3C)

assign cfg_en = (cbe_reg_l == 4'b1011 && idsel_reg == 1'b1) ? 1'b1 : 1'b0;
 
always @ (cfg_en or pci_irdy_l or pci_addr[7:0])
begin 
  if (cfg_en && !pci_irdy_l) begin 
    if (`write_04) begin 
      stat_com_en <= #1 1;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_10) begin 
      ba0_en <= #1 1;
      stat_com_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_14) begin 
      ba1_en <= #1 1;
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_3C) begin 
      int_line_en <= #1 1;
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      end
    else begin 
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
    end
  end
  else begin 
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
  end
end
 

 
  
/******************************************************************/
/************    Start Output Mux Section           ***************/
/******************************************************************/


always @ (posedge pci_clk or negedge pci_rst_l)
  begin 
    if (!pci_rst_l) begin 
	cfg_out <= #1 1'b0;
      end
      else if (cbe_reg_l == 4'b1010) begin 
	cfg_out <= #1 1'b1;
      end
      else begin
        cfg_out <= #1 1'b0;
      end
  end

always @ (cfg_dat_out or bkend_dat or cfg_out)
begin 
  if (cfg_out) begin 
      pci_dat_out <= #1 cfg_dat_out;
    end
  else
    begin 
      pci_dat_out <= #1 bkend_dat[31:0];    
    end
end




always @ (posedge pci_clk or negedge pci_rst_l)
begin 
  if (!pci_rst_l) begin 
        cfg_dat_out <= #1 32'b0; // zero at reset
      end
      else begin 
	//JO MOD decode from pci_addr[5:2] to [7:2] (256 byte)
	case (pci_addr [7:2])
	  6'b0000_00: cfg_dat_out <= #1 {DEVICE_ID,VENDOR_ID};// reg 00h (DevID/VendorID)
	  6'b0000_01: cfg_dat_out <= #1 {4'b0,stat11,DEV_SEL,9'b0,14'b0,com};//reg 04h (status/command)
	  6'b0000_10: cfg_dat_out <= #1 {CLASS_CODE,REVISION_ID}; // reg 08h (Class/revision)
	  6'b0000_11: cfg_dat_out <= #1 MISC_FUNCTIONS; // reg 0Ch (Misc Functions);
	  //JO MOD
	  //4'b01_00: cfg_dat_out <= #1 BA0; // reg 10h (Base Address 0);
	  6'b0001_00: cfg_dat_out <= #1 {ba0_rw_reg[31:4], 4'b1111} & BA0;
	  //4'b01_01: cfg_dat_out <= #1 BA1; // reg 14h (Base Address 1);
	  6'b0001_01: cfg_dat_out <= #1 {ba1_rw_reg[31:4], 4'b1111} & BA1;
	  //END JO MOD
	  6'b0010_11: cfg_dat_out <= #1 {SUB_SYSTEM_ID,SUB_VENDOR_ID}; // reg 2Ch (SubsystemID/Subsystem VendorID);
	  6'b0011_11: cfg_dat_out <= #1 {16'b0,INT_PIN,int_line}; // reg 3C (Max_Lat/Min_Gnt/Interrupt Pin/ Interupt Line);
	  default:  cfg_dat_out <= #1 32'b0; // unimplemented return 0's;
	endcase
      end

end



/******************************************************************/
/************    End Output Mux Section           ***************/
/******************************************************************/

 
    
endmodule //of config_mux