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// Copyright (c) 2001 by Lattice Semiconductor Corporation
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//   This VHDL or Verilog source code is intended as a design reference
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// Revision History :
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//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 1/20/98   :| Initial Creation
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//
//	Module  retry_count
/*
   This modules is the data retry counter.  Ifs the PCI Target responds with 
   a retry it must be done during the first data phase of a transaction.
   The target has up to 16 clock tics to respond with the first data phase
   or it must issue a retry.  This counter is enabled and reset from the
   statemachine block.  Once the target is ready to cycle data to the 
   bkend device it will assert base_region0_l or base_region1_l. 
   The bkend device must respond by asserting ready_l within 10 clock tics
   or else this counter block will assert the retry_l signal.  
*/
//

module  retry_count (pci_clk, count_rst_l, count_en_l, retry_l);
  output retry_l;
  input pci_clk, count_rst_l, count_en_l;
  
  reg [3:0] count;
 
  assign retry_l = (count >= 4'h9) ? 0 : 1;
  
    
  always @ (posedge pci_clk or negedge count_rst_l)
    begin 
      if (count_rst_l == 1'b0) begin 
        count = 4'h0;
      end
      else if (count_en_l == 1'b0) begin 
        count = count +1;
      end
      else begin 
	count = count;
      end
    end 
 
endmodule //of pargen