#-- Synplicity, Inc.
#-- Version Synplify 8.8A1
#-- Project file H:\fpga_test\fpga_fifo_0122_02\synthesis\run_options.txt
#-- Written on Wed May 07 16:22:43 2008


#add_file options
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v"
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology ProASIC3
set_option -part A3P125
set_option -package ""
set_option -speed_grade -2
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 1
set_option -retiming 0
set_option -report_path 4000
set_option -opcond Default
set_option -update_models_cp 0
set_option -preserve_registers 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "./fpga_core.edn"

#
#implementation attributes

set_option -vlog_std v2001
impl -active "synthesis"