?? lcd1602.fit.rpt
字號:
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 52 / 288 ( 18 % ) ;
; PIAs ; 59 / 288 ( 20 % ) ;
+----------------------------+-------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 7.38) ; Number of LABs (Total = 3) ;
+----------------------------------------------+-----------------------------+
; 0 - 2 ; 5 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 1 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 1 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 0 ;
; 33 - 35 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 5.38) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 5 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 6 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 1.63) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC6 ; ; LCD_RW ;
; A ; LC10 ; Current_State~42, Current_State~41, Current_State~45, Reset, Current_State~43, Current_State~44 ; LCD_Data[1]~reg0 ;
; A ; LC12 ; Current_State~45, Current_State~42, Current_State~44, Reset, Current_State~43, Current_State~41 ; LCD_Data[2]~reg0 ;
; A ; LC15 ; Current_State~42, Current_State~41, LCD_Data[4]~reg0, Current_State~43, Current_State~45, Reset, Current_State~44 ; LCD_Data[4]~reg0 ;
; A ; LC11 ; LCD_Data[1]~135, Current_State~42, Current_State~41, Reset, Current_State~43, Current_State~44, Current_State~45, LCD_Data[1]~reg0, Clk_Out ; LCD_Data[1]~reg0, LCD_Data[1] ;
; A ; LC5 ; Current_State~43, Current_State~44, Current_State~45, Current_State~41, Current_State~42, Clk_Out, Reset ; LCD_RS ;
; A ; LC9 ; LCD_Data[0]~104, LCD_Data[0]~105, LCD_Data[0]~106, LCD_Data[6]~138, Current_State~43, Current_State~41, Current_State~42, Current_State~44, Reset, LCD_Data[0]~reg0, Current_State~45, Clk_Out ; LCD_Data[0]~reg0, LCD_Data[0] ;
; A ; LC13 ; LCD_Data[2]~131, Current_State~45, Current_State~44, Reset, Current_State~43, Current_State~41, Current_State~42, LCD_Data[2]~reg0, Clk_Out ; LCD_Data[2]~reg0, LCD_Data[2] ;
; A ; LC14 ; LCD_Data[3]~69, LCD_Data[3]~70, LCD_Data[3]~71, LCD_Data[3]~72, Current_State~44, LCD_Data[3]~reg0, Current_State~41, Current_State~42, Current_State~43, Current_State~45, Reset, Clk_Out ; LCD_Data[3]~72, LCD_Data[3]~reg0, LCD_Data[3] ;
; A ; LC16 ; LCD_Data[4]~122, Current_State~41, Current_State~44, Reset, Current_State~43, Current_State~42, LCD_Data[4]~reg0, Clk_Out ; LCD_Data[4]~reg0, LCD_Data[4], LCD_Data[4]~122 ;
; A ; LC8 ; Clk, Reset, lpm_counter:Count_rtl_0|dffs[20], lpm_counter:Count_rtl_0|dffs[19], lpm_counter:Count_rtl_0|dffs[18], lpm_counter:Count_rtl_0|dffs[17], lpm_counter:Count_rtl_0|dffs[16], lpm_counter:Count_rtl_0|dffs[15], lpm_counter:Count_rtl_0|dffs[14], lpm_counter:Count_rtl_0|dffs[13], lpm_counter:Count_rtl_0|dffs[12], lpm_counter:Count_rtl_0|dffs[11], lpm_counter:Count_rtl_0|dffs[10], lpm_counter:Count_rtl_0|dffs[9], lpm_counter:Count_rtl_0|dffs[8], lpm_counter:Count_rtl_0|dffs[7], lpm_counter:Count_rtl_0|dffs[6], lpm_counter:Count_rtl_0|dffs[5], lpm_counter:Count_rtl_0|dffs[4], lpm_counter:Count_rtl_0|dffs[3], lpm_counter:Count_rtl_0|dffs[2], lpm_counter:Count_rtl_0|dffs[1], lpm_counter:Count_rtl_0|dffs[0] ; LCD_Data[4]~reg0, LCD_EN, Current_State~42, Current_State~44, Current_State~45, LCD_Data[5]~reg0, LCD_Data[3]~reg0, Current_State~41, Current_State~43, LCD_Data[7]~reg0, LCD_Data[6]~reg0, LCD_Data[2]~reg0, LCD_Data[0]~reg0, LCD_RS~reg0, LCD_Data[1]~reg0 ;
; A ; LC1 ; Clk, lpm_counter:Count_rtl_0|dffs[19], lpm_counter:Count_rtl_0|dffs[18], lpm_counter:Count_rtl_0|dffs[17], lpm_counter:Count_rtl_0|dffs[16], lpm_counter:Count_rtl_0|dffs[15], lpm_counter:Count_rtl_0|dffs[14], lpm_counter:Count_rtl_0|dffs[13], lpm_counter:Count_rtl_0|dffs[12], lpm_counter:Count_rtl_0|dffs[11], lpm_counter:Count_rtl_0|dffs[10], lpm_counter:Count_rtl_0|dffs[9], lpm_counter:Count_rtl_0|dffs[8], lpm_counter:Count_rtl_0|dffs[7], lpm_counter:Count_rtl_0|dffs[6], lpm_counter:Count_rtl_0|dffs[5], lpm_counter:Count_rtl_0|dffs[4], lpm_counter:Count_rtl_0|dffs[3], lpm_counter:Count_rtl_0|dffs[2], lpm_counter:Count_rtl_0|dffs[1], lpm_counter:Count_rtl_0|dffs[0], Reset ; Clk_Out ;
; A ; LC7 ; Clk, lpm_counter:Count_rtl_0|dffs[18], lpm_counter:Count_rtl_0|dffs[17], lpm_counter:Count_rtl_0|dffs[16], lpm_counter:Count_rtl_0|dffs[15], lpm_counter:Count_rtl_0|dffs[14], lpm_counter:Count_rtl_0|dffs[13], lpm_counter:Count_rtl_0|dffs[12], lpm_counter:Count_rtl_0|dffs[11], lpm_counter:Count_rtl_0|dffs[10], lpm_counter:Count_rtl_0|dffs[9], lpm_counter:Count_rtl_0|dffs[8], lpm_counter:Count_rtl_0|dffs[7], lpm_counter:Count_rtl_0|dffs[6], lpm_counter:Count_rtl_0|dffs[5], lpm_counter:Count_rtl_0|dffs[4], lpm_counter:Count_rtl_0|dffs[3], lpm_counter:Count_rtl_0|dffs[2], lpm_counter:Count_rtl_0|dffs[1], lpm_counter:Count_rtl_0|dffs[0], Reset ; lpm_counter:Count_rtl_0|dffs[20], Clk_Out ;
; A ; LC4 ; Clk, lpm_counter:Count_rtl_0|dffs[17], lpm_counter:Count_rtl_0|dffs[16], lpm_counter:Count_rtl_0|dffs[15], lpm_counter:Count_rtl_0|dffs[14], lpm_counter:Count_rtl_0|dffs[13], lpm_counter:Count_rtl_0|dffs[12], lpm_counter:Count_rtl_0|dffs[11], lpm_counter:Count_rtl_0|dffs[10], lpm_counter:Count_rtl_0|dffs[9], lpm_counter:Count_rtl_0|dffs[8], lpm_counter:Count_rtl_0|dffs[7], lpm_counter:Count_rtl_0|dffs[6], lpm_counter:Count_rtl_0|dffs[5], lpm_counter:Count_rtl_0|dffs[4], lpm_counter:Count_rtl_0|dffs[3], lpm_counter:Count_rtl_0|dffs[2], lpm_counter:Count_rtl_0|dffs[1], lpm_counter:Count_rtl_0|dffs[0], Reset ; lpm_counter:Count_rtl_0|dffs[19], lpm_counter:Count_rtl_0|dffs[20], Clk_Out ;
; A ; LC3 ; Clk, lpm_counter:Count_rtl_0|dffs[16], lpm_counter:Count_rtl_0|dffs[15], lpm_counter:Count_rtl_0|dffs[14], lpm_counter:Count_rtl_0|dffs[13], lpm_counter:Count_rtl_0|dffs[12], lpm_counter:Count_rtl_0|dffs[11], lpm_counter:Count_rtl_0|dffs[10], lpm_counter:Count_rtl_0|dffs[9], lpm_counter:Count_rtl_0|dffs[8], lpm_counter:Count_rtl_0|dffs[7], lpm_counter:Count_rtl_0|dffs[6], lpm_counter:Count_rtl_0|dffs[5], lpm_counter:Count_rtl_0|dffs[4], lpm_counter:Count_rtl_0|dffs[3], lpm_counter:Count_rtl_0|dffs[2], lpm_counter:Count_rtl_0|dffs[1], lpm_counter:Count_rtl_0|dffs[0], Reset ; lpm_counter:Count_rtl_0|dffs[18], lpm_counter:Count_rtl_0|dffs[19], lpm_counter:Count_rtl_0|dffs[20], Clk_Out ;
; A ; LC2 ; Clk, lpm_counter:Count_rtl_0|dffs[15],?? 快捷鍵說明
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