Timing Analyzer report for test_rec
Fri Oct 12 21:32:42 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
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and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                           ;
+------------------------------+-------+---------------+----------------------------------+---------------+------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From          ; To               ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------+------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 8.936 ns                         ; rxd           ; state[1]~reg0    ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.887 ns                         ; state[0]~reg0 ; state[0]         ; clk        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -5.090 ns                        ; rxd           ; data_out[0]~reg0 ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 201.37 MHz ( period = 4.966 ns ) ; state[0]~reg0 ; state[1]~reg0    ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;               ;                  ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------+------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                       ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From             ; To               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 201.37 MHz ( period = 4.966 ns )               ; state[0]~reg0    ; state[1]~reg0    ; clk        ; clk      ; None                        ; None                      ; 4.705 ns                ;
; N/A   ; 201.86 MHz ( period = 4.954 ns )               ; num[1]           ; state[0]~reg0    ; clk        ; clk      ; None                        ; None                      ; 4.693 ns                ;
; N/A   ; 208.29 MHz ( period = 4.801 ns )               ; num[2]           ; state[0]~reg0    ; clk        ; clk      ; None                        ; None                      ; 4.540 ns                ;
; N/A   ; 210.93 MHz ( period = 4.741 ns )               ; state[1]~reg0    ; state[1]~reg0    ; clk        ; clk      ; None                        ; None                      ; 4.480 ns                ;
; N/A   ; 214.04 MHz ( period = 4.672 ns )               ; state[0]~reg0    ; num[2]           ; clk        ; clk      ; None                        ; None                      ; 4.411 ns                ;
; N/A   ; 214.32 MHz ( period = 4.666 ns )               ; state[0]~reg0    ; num[1]           ; clk        ; clk      ; None                        ; None                      ; 4.405 ns                ;
; N/A   ; 214.50 MHz ( period = 4.662 ns )               ; state[0]~reg0    ; num[0]           ; clk        ; clk      ; None                        ; None                      ; 4.401 ns                ;
; N/A   ; 219.73 MHz ( period = 4.551 ns )               ; state[0]~reg0    ; bit[1]           ; clk        ; clk      ; None                        ; None                      ; 4.290 ns                ;
; N/A   ; 219.83 MHz ( period = 4.549 ns )               ; state[0]~reg0    ; bit[0]           ; clk        ; clk      ; None                        ; None                      ; 4.288 ns                ;
; N/A   ; 221.73 MHz ( period = 4.510 ns )               ; num[0]           ; state[0]~reg0    ; clk        ; clk      ; None                        ; None                      ; 4.249 ns                ;