?? fx2_to_extsram.lst
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C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE FX2_TO_EXTSRAM
OBJECT MODULE PLACED IN FX2_to_extSRAM.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE FX2_to_extSRAM.c BROWSE DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: FX2_to_extsyncFIFO.c
4 // Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
5 // interface using CY4265-15AC
6 //
7 // Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
8 //-----------------------------------------------------------------------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h"
12 #include "user.h"
13
14 #define EXTSRAMRDEN GPIFREADYSTAT & bmBIT0 //RDY0
15 //#define EXTSRAMWREN GPIFREADYSTAT & bmBIT0 //RDY0
16
17 #define GPIFTRIGRD 4
18
19 #define GPIF_EP2 0
20 #define GPIF_EP4 1
21 #define GPIF_EP6 2
22 #define GPIF_EP8 3
23
24 extern BOOL GotSUD; // Received setup data flag
25 extern BOOL Sleep;
26 extern BOOL Rwuen;
27 extern BOOL Selfpwr;
28
29 BYTE Configuration; // Current configuration
30 BYTE AlternateSetting; // Alternate settings
31 BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
32 extern const char xdata FlowStates[36];
33
34 BOOL in_enable = FALSE; // flag to enable IN transfers
35 BOOL IN_STOP_FLAG = FALSE; // flag to disable IN transfers
36 BOOL out_enable = FALSE; // flag to enable OUT transfers
37 BOOL OUT_STOP_FLAG = FALSE; // flag to disable OUT transfers
38 BOOL PAUSE_FLAG = FALSE; // flag to pause OUT transfers
39
40 int usb_RD_CNT = 0x0;
41
42 //-----------------------------------------------------------------------------
43 // Task Dispatcher hooks
44 // The following hooks are called by the task dispatcher.
45 //-----------------------------------------------------------------------------
46 void Setup_FLOWSTATE_Write ( void );
47 void Setup_FLOWSTATE_Read ( void );
48 void GpifInit ();
49
50 void TD_Init(void) // Called once at startup
51 {
52 1 // set the CPU clock to 48MHz
53 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
54 1 SYNCDELAY;
55 1
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 2
56 1 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
57 1 SYNCDELAY;
58 1 EP4CFG = 0x00; // EP4 not valid
59 1 SYNCDELAY;
60 1 EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
61 1 SYNCDELAY;
62 1 EP8CFG = 0x00; // EP8 not valid
63 1 SYNCDELAY;
64 1
65 1
66 1 FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
67 1 SYNCDELAY;
68 1 FIFORESET = 0x02; // reset EP2 FIFO
69 1 SYNCDELAY;
70 1 FIFORESET = 0x06; // reset EP6 FIFO
71 1 SYNCDELAY;
72 1 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
73 1 SYNCDELAY;
74 1
75 1 EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
76 1 SYNCDELAY;
77 1 EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
78 1 SYNCDELAY;
79 1 EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
80 1 SYNCDELAY;
81 1
82 1 GpifInit (); // initialize GPIF registers
83 1
84 1 SYNCDELAY;
85 1 EP2FIFOPFH = 0x88; //PAE = (<=1024)
86 1 SYNCDELAY;
87 1 EP2FIFOPFL = 0x0;
88 1 SYNCDELAY;
89 1 EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
90 1 SYNCDELAY;
91 1 // EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
92 1 // SYNCDELAY;
93 1 EP6FIFOPFH = 0x10; //PAF = (<=2 * 512)
94 1 SYNCDELAY;
95 1 EP6FIFOPFL = 0x0;
96 1 SYNCDELAY;
97 1 EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses PAF flag
98 1 SYNCDELAY;
99 1
100 1 // global flowstate register initializations
101 1
102 1 FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag)
103 1 SYNCDELAY;
104 1 FLOWSTB = FlowStates[23]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe
105 1 SYNCDELAY;
106 1 GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK
107 1 SYNCDELAY;
108 1 FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock
109 1 SYNCDELAY;
110 1 FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period
111 1 SYNCDELAY;
112 1
113 1
114 1 //port A as output io
115 1 PORTACFG =0x00;
116 1 OEA = 0xFF; // turn on PA as output pin
117 1 IOA &=0xEF; // bring PA4 low
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 3
118 1 SYNCDELAY;
119 1 IOA |= 0x10; // bring PA4 high(usb reset)
120 1
121 1 }
122
123 void TD_Poll(void)
124 {
125 1 //OUTPUT
126 1 if(out_enable) // if OUT transfers are enabled
127 1 {
128 2 if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
129 2 {
130 3 if(OUT_STOP_FLAG)
131 3 {
132 4 OUT_STOP_FLAG = FALSE;
133 4 out_enable = FALSE;
134 4 IOA |=0x08;
135 4 }
136 3
137 3 if ( ( EP24FIFOFLGS & 0x04 ) ) // if there's a packet >1024 bytes for EP2
138 3 {
139 4 //if ( EXTSRAMWREN) // if the external SRAM enable write
140 4 //{
141 4 IOA &= 0xEF; // bring PA4 high(usb reset)
142 4 /* if(enum_high_speed)
143 4 {
144 4 SYNCDELAY;
145 4 GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x0100)
146 4 SYNCDELAY;
147 4 GPIFTCB0 = 0x00;
148 4 SYNCDELAY;
149 4 }
150 4 else
151 4 {
152 4 SYNCDELAY;
153 4 GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x20)
154 4 SYNCDELAY;
155 4 GPIFTCB0 = 0x00;
156 4 SYNCDELAY;
157 4 }
158 4 */ SYNCDELAY;
159 4 GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x0100)
160 4 SYNCDELAY;
161 4 GPIFTCB0 = 0x00;
162 4 SYNCDELAY;
163 4 Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation
164 4 SYNCDELAY;
165 4 GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
166 4 SYNCDELAY;
167 4 IOA |=0x08;
168 4
169 4 //}
170 4 }
171 3 }
172 2 }
173 1 //INPUT FIFO
174 1 if(in_enable) // if IN transfers are enabled
175 1 {
176 2 if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
177 2 {
178 3 if(IN_STOP_FLAG)
179 3 {
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 4
180 4 IN_STOP_FLAG = FALSE;
181 4 in_enable = FALSE;
182 4 }
183 3 if ( EXTSRAMRDEN ) // if external sram enable read
184 3 {
185 4 if ( ( EP68FIFOFLGS & 0x04 ) ) // if EP6 FIFO is <1024
186 4 {
187 5 if(enum_high_speed)
188 5 { PA3=1 ;
189 6 SYNCDELAY;
190 6 GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x01
-00)
191 6 SYNCDELAY;
192 6 GPIFTCB0 = 0x00;
193 6 SYNCDELAY;
194 6 }
195 5 else
196 5 {
197 6 SYNCDELAY;
198 6 GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x20)
199 6 SYNCDELAY;
200 6 GPIFTCB0 = 0x00;
201 6 SYNCDELAY;
202 6 }
203 5
204 5 Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
205 5 SYNCDELAY;
206 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
207 5 SYNCDELAY;
208 5 /* usb_RD_CNT++;
209 5 if( usb_RD_CNT >=256 ) //32kbytes
210 5 {
211 5 usb_RD_CNT = 0;
212 5
213 5 //send usb_rd_end signal to cpld to idle state of lsm
214 5 IOA &= 0xFB; // bring PA2 low
215 5 IOA |= 0x04; // pull PA2 high initially
216 5 EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
217 5 IOA &= 0xFB; // bring PA2 low
218 5 //reset fifo of ep6
219 5 FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
220 5 SYNCDELAY;
221 5 FIFORESET = 0x06; // reset EP6 FIFO
222 5 SYNCDELAY;
223 5 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
224 5 SYNCDELAY;
225 5 }
226 5 */
227 5 }
228 4 }
229 3 }
230 2 }
231 1 }
232
233 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
234 {
235 1 return(TRUE);
236 1 }
237
238 BOOL TD_Resume(void) // Called after the device resumes
239 {
240 1 return(TRUE);
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 5
241 1 }
242
243 //-----------------------------------------------------------------------------
244 // Device Request hooks
245 // The following hooks are called by the end point 0 device request parser.
246 //-----------------------------------------------------------------------------
247
248 BOOL DR_GetDescriptor(void)
249 {
250 1 return(TRUE);
251 1 }
252
253 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
254 {
255 1 if( EZUSB_HIGHSPEED( ) )
256 1 { // FX2 enumerated at high speed
257 2 SYNCDELAY; //
258 2 EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
259 2 SYNCDELAY; //
260 2 EP6AUTOINLENL = 0x00;
261 2 SYNCDELAY;
262 2 enum_high_speed = TRUE;
263 2 }
264 1 else
265 1 { // FX2 enumerated at full speed
266 2 SYNCDELAY;
267 2 EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
268 2 SYNCDELAY;
269 2 EP6AUTOINLENL = 0x40;
270 2 SYNCDELAY;
271 2 enum_high_speed = FALSE;
272 2 }
273 1
274 1 Configuration = SETUPDAT[2];
275 1 return(TRUE); // Handled by user code
276 1 }
277
278 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
279 {
280 1 EP0BUF[0] = Configuration;
281 1 EP0BCH = 0;
282 1 EP0BCL = 1;
283 1 return(TRUE); // Handled by user code
284 1 }
285
286 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
287 {
288 1 AlternateSetting = SETUPDAT[2];
289 1 return(TRUE); // Handled by user code
290 1 }
291
292 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
293 {
294 1 EP0BUF[0] = AlternateSetting;
295 1 EP0BCH = 0;
296 1 EP0BCL = 1;
297 1 return(TRUE); // Handled by user code
298 1 }
299
300 BOOL DR_GetStatus(void)
301 {
302 1 return(TRUE);
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 6
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