?? fx2_to_extsram.c
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#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: FX2_to_extsyncFIFO.c
// Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
// interface using CY4265-15AC
//
// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"
#include "user.h"
#define EXTSRAMRDEN GPIFREADYSTAT & bmBIT0 //RDY0
//#define EXTSRAMWREN GPIFREADYSTAT & bmBIT0 //RDY0
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
extern const char xdata FlowStates[36];
BOOL in_enable = FALSE; // flag to enable IN transfers
BOOL IN_STOP_FLAG = FALSE; // flag to disable IN transfers
BOOL out_enable = FALSE; // flag to enable OUT transfers
BOOL OUT_STOP_FLAG = FALSE; // flag to disable OUT transfers
BOOL PAUSE_FLAG = FALSE; // flag to pause OUT transfers
int usb_RD_CNT = 0x0;
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void Setup_FLOWSTATE_Write ( void );
void Setup_FLOWSTATE_Read ( void );
void GpifInit ();
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
SYNCDELAY;
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
SYNCDELAY;
EP4CFG = 0x00; // EP4 not valid
SYNCDELAY;
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 not valid
SYNCDELAY;
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
GpifInit (); // initialize GPIF registers
SYNCDELAY;
EP2FIFOPFH = 0x88; //PAE = (<=1024)
SYNCDELAY;
EP2FIFOPFL = 0x0;
SYNCDELAY;
EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
SYNCDELAY;
// EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
// SYNCDELAY;
EP6FIFOPFH = 0x10; //PAF = (<=2 * 512)
SYNCDELAY;
EP6FIFOPFL = 0x0;
SYNCDELAY;
EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses PAF flag
SYNCDELAY;
// global flowstate register initializations
FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag)
SYNCDELAY;
FLOWSTB = FlowStates[23]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe
SYNCDELAY;
GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK
SYNCDELAY;
FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock
SYNCDELAY;
FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period
SYNCDELAY;
//port A as output io
PORTACFG =0x00;
OEA = 0xFF; // turn on PA as output pin
IOA &=0xEF; // bring PA4 low
SYNCDELAY;
IOA |= 0x10; // bring PA4 high(usb reset)
}
void TD_Poll(void)
{
//OUTPUT
if(out_enable) // if OUT transfers are enabled
{
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if(OUT_STOP_FLAG)
{
OUT_STOP_FLAG = FALSE;
out_enable = FALSE;
IOA |=0x08;
}
if ( ( EP24FIFOFLGS & 0x04 ) ) // if there's a packet >1024 bytes for EP2
{
//if ( EXTSRAMWREN) // if the external SRAM enable write
//{
IOA &= 0xEF; // bring PA4 high(usb reset)
/* if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
*/ SYNCDELAY;
GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation
SYNCDELAY;
GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
IOA |=0x08;
//}
}
}
}
//INPUT FIFO
if(in_enable) // if IN transfers are enabled
{
if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if(IN_STOP_FLAG)
{
IN_STOP_FLAG = FALSE;
in_enable = FALSE;
}
if ( EXTSRAMRDEN ) // if external sram enable read
{
if ( ( EP68FIFOFLGS & 0x04 ) ) // if EP6 FIFO is <1024
{
if(enum_high_speed)
{ PA3=1 ;
SYNCDELAY;
GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x02; // setup transaction count (2*512 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
SYNCDELAY;
/* usb_RD_CNT++;
if( usb_RD_CNT >=256 ) //32kbytes
{
usb_RD_CNT = 0;
//send usb_rd_end signal to cpld to idle state of lsm
IOA &= 0xFB; // bring PA2 low
IOA |= 0x04; // pull PA2 high initially
EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
IOA &= 0xFB; // bring PA2 low
//reset fifo of ep6
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
}
*/
}
}
}
}
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
if( EZUSB_HIGHSPEED( ) )
{ // FX2 enumerated at high speed
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
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