//*******************************************************************************************************************************************  // COMPACT FLASH  // March 2007//*******************************************************************************************************************************************//Top modulemodule compact_flash( //Input signals for the compact flash card                      host_address,           //Address bus                        ce_1,                   //Active low Card select signal                       iord,                   //Active low I/O read strobe                      iowr,                   //Active low I/O write strobe                      oe,                     //Active low Output enable strobe                      reset,                  //Reset the compact flash card                       reg_1,                  //Low during I/O operations,in memory mode used to distinguish betwen common and attribute memory                      we,                     //Active low signal used for writing configuration registers                                           //Input signals for the compact flash interface                      h_enable,               //Chip enable                      h_ack,                  //Acknowledgement to the interrupt request made by the interface                      h_control,              //Selecting between I/O and memory READ/WRITE operations                      h_reset,                //Hardware and software reset					  h_iom ,                 //Selecting between I/O and Memory mode                        h_address,              //Address bus from the host to the interface                                             //Output signals of the compact flash card		              ready,                  //Asserted low during power up or reset,and made high in the memory mode to show that it's ready to accept data		              cd_1,                   //Active low Card detect siganls 	                  ireq,            		  //Interrrupt request from I/O device			          			          //Output signals of the compact flash interface			          h_int,                  //Interrupt siganl for the host 			          h_ready                 //Indicates the status of the CF+ card			                   );            				output [10:0] host_address;		output [1:0] ce_1;		output we;		output reg_1;		output iord;		output iowr;		output reset;		output oe;		output h_int;		output h_ready;						input [1:0] h_reset;		input [10:0] h_address;					input [3:0] h_control;		input [1:0] cd_1;		input h_ack;		input h_enable;		input ready;		input h_iom;		input ireq;						wire h_ready;		wire ready_int;		wire hint_int;		wire hint_n0;		wire [10:0] h_address;						reg  [10:0] host_address;        reg  [1:0]  ce_1;		reg  we;		reg  reg_1;		reg  iord;		reg  iowr;		reg  reset;		reg  oe;		reg  ready_n;		initial      begin		  host_address=11'bxxxxxx00000;          ce_1=2'bx0;		  we=1;		  reg_1=0;		  iord=0;		  iowr=1;		  oe=0;			end						assign ready_int = ready_n;		assign h_ready = ready_int;	   assign  h_int = (~cd_1[0] & ~cd_1[1] & h_enable) ? 1'b0 : 1'b1 ;        //All assignments are synchronized to the positive of the acknowledgement signalalways @(posedge h_ack )         begin            //As long as acknowledgement siganl is high the process continues   if (h_reset==2'b11)           begin            //Hardware reset,so the acknowledgement is made low         reset=1'b1;       ce_1=2'bx0;       reg_1=1'b0;       oe=1'b0;       we=1'b1;       host_address[10:5]=6'b111111;       host_address[4:0]=5'b00000;                                                      end   else if(h_iom == 0)             begin                   //Checking for memory mode          reset=1'b0;                       if(ready==1'b1)          begin          if(h_control==4'b0000)begin                    //Configuration option register read                 			   ce_1=2'bx0;               reg_1=1'b0;               oe=1'b0;               we=1'b1;               host_address[10:5]=6'bxxxxxx;               host_address[4:0]=5'b00000;            end     if((h_control==4'b0001)&(h_reset==2'b00))        begin                     //Configuration option register write             reset=1'b1;                                      //Software reset ,so the acknowledgement goes low             ce_1=2'bx0;             reg_1=1'b0;             oe=1'b0;             we=1'b1;             host_address[10:5]=6'bxxxxxx;             host_address[4:0]=5'b00000;                      end                                  //An interrupt is generated by the interface to continue with the process further                 if(h_control==4'b0001) begin             ce_1=2'bx0;             reg_1=1'b0;             oe=1'b1;             we=1'b0;             host_address[10:5]=6'bxxxxxx;             host_address[4:0]=5'b00000;                end                        if(h_control==4'b0010)        begin                   //Card status register read           ce_1=2'bx0;           reg_1=1'b0;           oe=1'b0;           we=1'b1;           host_address[10:5]=6'bxxxxxx;           host_address[4:0]=5'b00010;        end            if(h_control==4'b0011)         begin                   //Card status register write            ce_1=2'bx0;           reg_1=1'b0;           oe=1'b1;           we=1'b0;           host_address[10:5]=6'bxxxxxx;           host_address[4:0]=5'b00010;        end      if(h_control==4'b0100)          begin                  //Pin replacement register read          ce_1=2'bx0;          reg_1=1'b0;          oe=1'b0;          we=1'b1;          host_address[10:5]=6'bxxxxxx;          host_address[4:0]=5'b00100;        end      if(h_control==4'b0101)           begin                 //Pin replacement register write          ce_1=2'bx0;          reg_1=1'b0;          oe=1'b1;          we=1'b0;          host_address[10:5]=6'bxxxxxx;          host_address[4:0]=5'b00100;       end      if(h_control==4'b0110)            begin               //Common memory read (8 bit D7-d0)          ce_1=2'b10;          reg_1=1'b1;          oe=1'b0;          we=1'b1;          host_address[10:0]=h_address[10:0];        end        if(h_control==4'b0111)           begin               //Common memory read (8 bit D15-D8)           ce_1=2'b01;           reg_1=1'b1;           oe=1'b0;           we=1'b1;           host_address[10:0]=h_address[10:0];        end        if(h_control==4'b1100)           begin               //Common memory read (16 bit D15-D0)          ce_1=2'b00;          reg_1=1'b1;          oe=1'b0;          we=1'b1;          host_address[10:1]=h_address[10:1];          host_address[0]=1'b0;        end       if(h_control==4'b1000)           begin                //Common memory write(8 bit D7-D0)           ce_1=2'b10;           reg_1=1'b1;           oe=1'b1;           we=1'b0;           host_address[10:0]=h_address[10:0];        end        if(h_control==4'b1001)           begin                //Common memory write(8 bit D15-D8)           ce_1=2'b01;           reg_1=1'b1;           oe=1'b1;           we=1'b0;           host_address[10:0]=h_address[10:0];        end       if(h_control==4'b1010)            begin               //Common memory write(16 bit D15-D0)            ce_1=2'b00;          reg_1=1'b1;          oe=1'b1;          we=1'b0;          host_address[10:1]=h_address[10:1];          host_address[0]=1'b0;       end       if(h_control==4'b1011)            begin               //Card information structure read          ce_1=2'bx0;          reg_1=1'b0;          oe=1'b0;          we=1'b1;          host_address[10:1]=10'bxxxxxxxxxx;          host_address[0]=1'b0;               end                    end            ready_n=ready;                          end   else if((ireq==1)&(h_iom==1))    begin             //Checking for I/O mode		   reset=1'b0;         if(h_control==4'b0000)          begin             //I/O base 0 register               ce_1=2'bx0;             reg_1=1'b0;             oe=1'b1;             we=1'b0;             host_address[10:5]=6'bxxxxxx;             host_address[4:0]=5'b01010;          end          if(h_control==4'b0001)           begin             //I/O base 1 register               ce_1=2'bx0;             reg_1=1'b0;             oe=1'b0;                                            we=1'b1;             host_address[10:5]=6'bxxxxx;             host_address[4:0]=5'b01100;          end         if(h_control==4'b0010)           begin             //I/O limit               ce_1=2'bx0;             reg_1=1'b0;             oe=1'b1;             we=1'b0;             host_address[10:5]=6'bxxxxxx;             host_address[4:0]=5'b10010;          end           if(h_control==4'b0011)          begin            //I/O mode single  byte input access (8 bits)               ce_1=2'b10;              reg_1=1'b0;              iord=1'b0;              iowr=1'b1;              host_address[0]=1'b0;           end          if(h_control==4'b0100)          begin            //I/O mode single byte output access (8 bits)             ce_1=2'b10;             reg_1=1'b0;             iord=1'b1;             iowr=1'b0;             host_address[0]=1'b0;          end          if(h_control==4'b0101)          begin            //I/O mode word input access (16 bits)               ce_1=2'b00;             reg_1=1'b0;             iord=1'b0;             iowr=1'b1;             host_address[0]=1'b0;          end          if(h_control==4'b0110)          begin            //I/O mode word output access (16 bits)             ce_1=2'b00;             reg_1=1'b0;             iord=1'b1;             iowr=1'b0;             host_address[0]=1'b0;          end          if(h_control==4'b0111)          begin            //I/O read inhibit               ce_1=2'bxx;             reg_1=1'b1;             iord=1'b0;             iowr=1'b1;             host_address[0]=1'bx;          end          if(h_control==4'b1000)           begin           //I/O write inhibit               ce_1=2'bxx;             reg_1=1'b1;             iord=1'b1;             iowr=1'b0;             host_address[0]=1'bx;          end         if(h_control==4'b1001)             begin          //High byte input only            ce_1=2'b10;            reg_1=1'b0;            iord=1'b0;            iowr=1'b1;            host_address[0]=1'bx;         end         if(h_control==4'b1010)             begin          //High byte output only             ce_1=2'b10;            reg_1=1'b0;            iord=1'b1;            iowr=1'b0;            host_address[0]=1'bx;         end             end                end                    endmodule