INCLUDE   AT91RM9200.inc_STACK_BASEADDRESS	EQU 0x21ff8000_MMUTT_STARTADDRESS	EQU 0x21ff8000;_ISR_STARTADDRESS	EQU 0x10040000_ISR_STARTADDRESS	EQU 0x21ffff00;Pre-defined constantsUSERMODE    EQU 	0x10FIQMODE     EQU 	0x11IRQMODE     EQU 	0x12SVCMODE     EQU 	0x13ABORTMODE   EQU 	0x17UNDEFMODE   EQU 	0x1bMODEMASK    EQU 	0x1fNOINT       EQU 	0xc0I_BIT	EQU	0x80F_BIT	EQU	0x40T_BIT	EQU	0x20	AREA	reset, CODE, READONLY		ENTRY		EXPORT	__ENTRY__ENTRY	ResetEntry	b	ResetHandler	ldr	pc, =HandlerUndef		;handler for Undefined mode	ldr	pc, =HandlerSWI			;handler for SWI interrupt	ldr	pc, =HandlerPabort		;handler for PAbort	ldr	pc, =HandlerDabort		;handler for DAbort	ldr	pc, =.					;reserved	ldr	pc, =HandlerIRQ			;handler for IRQ interrupt;	ldr	pc, [pc,#-0xF20]		;IRQ : read the AIC	ldr	pc, =HandlerFIQ			;handler for FIQ interrupt		EXPORT	this_machine_ipthis_machine_ip	DCD	(192<<24)|(168<<16)|(2<<8)|(223)    	MACRO$HandlerLabel HANDLER $HandleLabel$HandlerLabel	sub	sp, sp, #4			;decrement sp(to store jump address)	stmfd	sp!, {r0}		;PUSH the work register to stack(lr does't push because it return to original address)	ldr	r0, =$HandleLabel	;load the address of HandleXXX to r0	ldr	r0, [r0]			;load the contents(service routine start address) of HandleXXX	str	r0, [sp, #4]      	;store the contents(ISR) of HandleXXX to stack	ldmfd	sp!, {r0, pc}	;POP the work register and pc(jump to ISR)	MEND	LTORG   HandlerFIQ      HANDLER HandleFIQHandlerIRQ      HANDLER HandleIRQHandlerUndef    HANDLER HandleUndefHandlerSWI      HANDLER HandleSWIHandlerDabort   HANDLER HandleDabortHandlerPabort   HANDLER HandlePabortIsrIRQ	sub	sp, sp, #4       ;reserved for PC	stmfd	sp!,{r8-r9}		ldr	r9, =AT91C_BASE_AIC	mov	r8, r9	ldr	r9, [r9, #AIC_ISR]	and	r9, r9, #0x1f	add	r8, r8, r9, lsl #2	ldr	r8, [r8, #AIC_SVR]	str	r8, [sp, #8]	ldmfd	sp!,{r8-r9,pc}	; * the actual reset codeResetHandler	;Set up User Mode, set User Mode Stack and disable interrupts		msr	CPSR_c, #(SVCMODE|I_BIT|F_BIT)	;------------------------------------------------------------------------------;Step 1.;------------------------------------------------------------------------------;-Enabling the Main Oscillator;-Normally First instruction in PMC initialisation;------------------------------------------------------------------------------;-Main oscillator Enable register	APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF	ldr     r1, = AT91C_BASE_CKGR	; Get the CKGR Base Address	ldr 	r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT	str     r0, [r1, #CKGR_MOR]		; set the cpu to SVC32 mode	;	mrs	r0, cpsr;	bic	r0, r0, #0x1f;	orr	r0, r0, #0x13;	msr	cpsr_cf, r0			; relocate exeception table	 	adr	r0, ResetEntry	mov	r1, #0	mov	r2, #16copyex	subs	r2, r2, #1	ldr	r3, [r0], #4	str	r3, [r1], #4	bne	copyex			IMPORT	LowLevelInit	;	ldr	r1, =0x204000;=SVCStack;	bic	r1, r1, #3				; Insure word alignement;	mov	sp, r1					; Init stack SYS	mov	sp, #0x204000		bl 	LowLevelInit		;Initialize stacks	bl	InitStacks	copy_proc_beg	adr	r0, ResetEntry	ldr	r2, BaseOfROM	cmp	r0, r2	ldreq	r0, TopOfROM	beq	InitRam		ldr r3, TopOfROM0		ldmia	r0!, {r4-r7}	stmia	r2!, {r4-r7}	cmp	r2, r3	bcc	%B0		sub	r2, r2, r3	sub	r0, r0, r2						InitRam		ldr	r2, BaseOfBSS	ldr	r3, BaseOfZero	0	cmp	r2, r3	ldrcc	r1, [r0], #4	strcc	r1, [r2], #4	bcc	%B0		mov	r0,	#0	ldr	r3,	EndOfBSS1		cmp	r2,	r3	strcc	r0, [r2], #4	bcc	%B1		IMPORT	irq_handler  	; Setup IRQ handler	ldr	r0, =HandleIRQ			;This routine is needed	ldr	r1, =IsrIRQ			;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c	ldr	r1, =irq_handler	str	r1, [r0]	IMPORT	main_main__main	EXPORT	_main	EXPORT	__main;	swi	0x1234		;test swi	ldr	r0, =main	mov	lr, pc	bx	r0		b	.;===========================================================;The location of stacksUserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~ SVCStack	EQU	(_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~UndefStack	EQU	(_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~AbortStack	EQU	(_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~IRQStack	EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~ ;function initializing stacksInitStacks	;Don't use DRAM,such as stmfd,ldmfd......	;SVCstack is initialized before	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'	mrs	r0,cpsr	bic	r0,r0,#MODEMASK	orr	r1,r0,#UNDEFMODE|NOINT	msr	cpsr_cxsf,r1		;UndefMode	ldr	sp,=UndefStack		orr	r1,r0,#ABORTMODE|NOINT	msr	cpsr_cxsf,r1		;AbortMode	ldr	sp,=AbortStack	orr	r1,r0,#IRQMODE|NOINT	msr	cpsr_cxsf,r1		;IRQMode	ldr	sp,=IRQStack    	orr	r1,r0,#FIQMODE|NOINT	msr	cpsr_cxsf,r1		;FIQMode	ldr	sp,=FIQStack	bic	r0,r0,#MODEMASK|NOINT	orr	r1,r0,#SVCMODE	msr	cpsr_cxsf,r1		;SVCMode	ldr	sp,=SVCStack		;USER mode has not be initialized.		mov	pc,lr 	;The LR register won't be valid if the current mode is not SVC mode.;===========================================================		IMPORT  |Image$$RO$$Base|	; Base of ROM code	IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)	IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise	IMPORT  |Image$$ZI$$Base|   ; Base and limit of area	IMPORT  |Image$$ZI$$Limit|  ; to zero initialise	BaseOfROM	DCD	|Image$$RO$$Base|TopOfROM	DCD	|Image$$RO$$Limit|BaseOfBSS	DCD	|Image$$RW$$Base|BaseOfZero	DCD	|Image$$ZI$$Base|EndOfBSS	DCD	|Image$$ZI$$Limit|		ALIGN			EXPORT DisableIntDisableInt	mrs	r0,	cpsr	orr	r0,	r0, #0xc0	msr	cpsr_cf, r0	mov	pc,	lr		    	AREA RamData, DATA, READWRITE        ^   _ISR_STARTADDRESSHandleReset 	#   4HandleUndef 	#   4HandleSWI   	#   4HandlePabort    #   4HandleDabort    #   4HandleReserved  #   4HandleIRQ   	#   4HandleFIQ   	#   4;Don't use the label 'IntVectorTable',;The value of IntVectorTable is different with the address you think it may be.;IntVectorTableHandleEINT0   	#   4HandleEINT1   	#   4HandleEINT2   	#   4HandleEINT3   	#   4HandleEINT4_7	#   4HandleEINT8_23	#   4HandleRSV6	#   4HandleBATFLT   	#   4HandleTICK   	#   4HandleWDT	#   4HandleTIMER0 	#   4HandleTIMER1 	#   4HandleTIMER2 	#   4HandleTIMER3 	#   4HandleTIMER4 	#   4HandleUART2  	#   4HandleLCD 	#   4HandleDMA0	#   4HandleDMA1	#   4HandleDMA2	#   4HandleDMA3	#   4HandleMMC	#   4HandleSPI0	#   4HandleUART1	#   4HandleRSV24	#   4HandleUSBD	#   4HandleUSBH	#   4HandleIIC   	#   4HandleUART0 	#   4HandleSPI1 	#   4HandleRTC 	#   4HandleADC 	#   4	END