This is the fpga implementation of the ARM processor.  The memoryconfiguration is the main change.  The cache sizes had to be alteredto fit into the standard Xilinx Virtex FPGA.  This is designed to berun on a STARFIRE board from Annapolis Microsystems.  The VHDL modelsrepresent the necessary interfaces to fit the ARM into the STARFIRE system.Verilog File    Description:==================================================================align.v         Data Aligner for Byte/Halfword/Word Accessalu.v           ALUarm9.v          ARM Processor Top Level Modulecomp42_2.v      4-2 Compressor used in Multipliercomp42_n40.v    Level 0 Bank of Compressors (40 of comp42_2)comp42_n64.v    Level 1 Bank of Compressors (64 of comp42_2)counters.v      Performance Counters (IMISS, DMISS, ...)control.v       Instantiates the ifetch, interlock, and counters blocksdcache.v        Data Cache Controllerdecode.v	A 4:16 Decoderdtag.v		Simulation Model for Data Tagsdtag_synth.v	Synthesis Model for the Data Tagsex.v            Execute Stage of Pipelineicache.v        Instruction Cache Controllerid.v            Instruction Decode Stage of Pipelineidt71v546s100.v ZBT SRAM modelifetch.v        Instruction Fetch and Branch Prediciton Unitinterlock.v     Stall Controlleritag.v		Simulation Model for Instruction Tagsitag_synth.v	Sythesis Model for Instruction Tagslec25dscc25.v   LEDA Library for synthesismainmem.v       Instantiates the SRAM mapreg.v        Maps Register Indexes by Modemapspsr.v       Maps SPSR Indexes by Modeme.v            Memory Stage of PIpelineminiram.v       Lock Down Cache (ROM) used for Decompressionmmu_new.v       Memory Management Unit and Decompression Controllermult.v          Multiplier top-level modulemultacc.v       32x8 multiplierpardef.*        Parameters and Define Statementspipe.v          Instantiates the Execute, Decode, and Memory Stagesppselect.v      Partial Product Select for Booth Recodingram1p.v         Simulation RAM model for Instruction Cacheram1p_synth.v   Synthesis RAM model for Instruction Cacheram2p.v 	Simulation RAM model for Data Cacheram2p_synth.v   Synthesis RAM model for Data Cacheregfile.v       Register Fileshifter.v       Shift Unittag.v           TAG model for cachesVHDL File       		Description:==================================================================clock_if_entarch.vhd		Standard Interface to Clocksclock_io_entarch.vhd		Clock Padshost.vhd			Simulates testarm.vhxhost_dcomp.vhd			Simulates Program with D/I Comphost_icomp.vhd			Simulates Program with I Comp io_conn_if_entarch.vhd		Standard Interface to I/O Cardlad_bus_if_entarch.vhd		Standard Interface to LAD Buslad_bus_io_entarch.vhd		LAD Bus Padsled_if_entarch.vhd		Standard Interface to LED'sled_io_entarch.vhd		LED Padsmem_if_entarch.vhd		Standard Interface to Memorymem_io_entarch.vhd		Memory Padsmezz_mem_card_cfg.vhd		Mezz Card Config for Simulationpe0_bus_if_entarch.vhd		Standard Interface to PE0-PEX Buspe0_bus_io_entarch.vhd		PE0-PEX Padspe_arm2mem_if_entarch.vhd	User Defined Interface from ARM to Memorype_lad2mem_if_entarch.vhd	Standard Interface from LAD to Memorype_mezz_mem_pkg.vhd		Mezzanine Package used in Synthesispe_pkg.vhd			Processing Element Package used in Synthesispex.vhd				User Defined Processing Element				Contains the ARM and all necessary I/F'spex_synth.vhd			Modified Library Use Clause for Synthesispex_ent.vhd			Entity Definition (I/O) for PEXpex_mezz_mem_if_entarch.vhd	Standard Interface to Mezzanine Memorypex_mezz_mem_io_entarch.vhd	Mezzanine Memory Padssystem_cfg.vhd			System Configuration for Simulationsystolic_if_entarch.vhd		Standard Interface to Systolic Bussystolic_io_entarch.vhd		Systolic Bus Padsxilinx_pkg.vhd			Xilinx Package used in Synthesis				Contains Definitions of User Defined Data TypesScript File		Description:==================================================================project_vcom.do		Compile Script for ModelSim (Run First)project_vsim.do		Simulation Script for ModelSim (Run Second)wave.do			Waveform Script for ModelSim (Load in Wave Window)pex.fes			FPGA Express Synthesis Script/*************************************************************************Below is the FPGA heirarchy -- Synthesis Heirarchy*************************************************************************/pex_synth.vhd  pe_arm2mem_if_entarch.vhd  pe_lad2mem_if_entarch.vhd  arm9.v     regfile.v     mmu.v         counters.v     icache.v        ram1p_synth.v        itag_synth.v         miniram.v     dcache.v        ram2p_synth.v         dtag_synth.v        control.v        ifetch.v        interlock.v     pipe.v        me.v           align.v        id.v           mapreg.v           decode.v        ex.v           alu.v           shifter.v           mapspsr.v           mult.v              multacc.v                 ppselect.v                 comp42_n40.v                    comp42_2.v                 comp42_n64.v                    comp42_2.v