-- Quartus VHDL Template
-- State Machine with Asynchronous Reset (1 block)
-- State Machine outputs will be registered

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY vhdl1 IS
	PORT
	(
		SWITCH_MODE:IN STD_LOGIC_VECTOR (1 DOWNTO 0);	
		FPGA_RESET: OUT	STD_LOGIC;
		CPU_RST,MCU_RST_CTRL	: IN	STD_LOGIC
	);
END vhdl1;

ARCHITECTURE rtl OF vhdl1 IS
BEGIN

	WITH SWITCH_MODE SELECT
		FPGA_RESET	<=	CPU_RST	WHEN	"00",
					MCU_RST_CTRL	WHEN	"01",
					MCU_RST_CTRL	WHEN	"10",
					MCU_RST_CTRL	WHEN	"11";

END rtl;