// Quartus Verilog Template
// Counter with synchronous load and active low asynchronous clear

module icpld	(
		input [2:0] SWITCH_MODE,RAM_ADDR_LATCH,
		input [3:0] RAM_DATA_SEL,MCU_CODE,
		input FREGSEL_LATCH_EN,
		output reg [3:0] RAM_EN,		
		output reg RAM_OE,RAM_WR,RAM_DATA_DIR,RAM_ADDR_LATCH_OE,FREGSEL_LATCH_OE,
		output reg FPGA2RAM_DATA_EN,FPGA2RAM_DATA_DIR,FPGA2RAM_ADDR_EN,FPGA_CLK,FPGA_RESET,
		output reg [1:0] DIPCTRL,
		output reg [11:0] MCU_SEL,
		input FPGA_RD,FPGA_WR,CPU_RST,EXT_CLK,MCU_RST_CTRL,MCU_CLK,MCU_RD,MCU_WR,SWCLK,

		input RXD_CPLD,RS_CLK,PS2KB_DATA,PS2MOUSE_DATA,
		output reg TXD_CPLD,		
		inout PS2KB_CLOCK,PS2MOUSE_CLOCK,
		output reg [2:0] LCD_CTRL,
		output reg [7:0] LCD_DATA,
		input [7:0] FPGA_ADDR, //FPGA_ADDR_(23:16)
		inout [7:0] FPGA_DATA,  //FPGA_DATA_(7:0)
		output reg [3:0] INTr	
	);
	
always @(*)
begin
case (SWITCH_MODE)
	3'b000 :
	begin
		FPGA_RESET = CPU_RST; 
		FPGA_CLK = SWCLK;
		FPGA2RAM_DATA_EN = 1;		
		FPGA2RAM_ADDR_EN = 1;
		RAM_OE = 1;				
		RAM_WR = 1;		
		RAM_EN = 4'b1111;
		RAM_ADDR_LATCH_OE = 1;
		MCU_SEL = 12'b111111111111;
		FREGSEL_LATCH_OE = 1;	
		DIPCTRL = 2'b00;			
	end
	3'b001:
	begin
		FPGA_RESET = CPU_RST; 
		FPGA_CLK = SWCLK;		
		FPGA2RAM_DATA_EN = 0;
		FPGA2RAM_ADDR_EN = 0;	
		if (FPGA_RD==0 && FPGA_WR==1)
		begin
			RAM_OE = 0;
			RAM_WR = 1;
			RAM_EN = 0;						
		end
		else if (FPGA_RD==1 && FPGA_WR==0)
		begin
			RAM_OE = 1;		
			RAM_WR = 0;
			RAM_EN = 0;			
		end		
		else if (FPGA_RD==1 && FPGA_WR==1)
		begin
			RAM_OE = 1;				
			RAM_WR = 1;
			RAM_EN = 4'b1111;			
		end				
		else
		begin
			RAM_OE = 1;
			RAM_WR = 1;			
			RAM_EN = 0;
		end
		RAM_ADDR_LATCH_OE = 1;	
		MCU_SEL = 12'b111111111111;			
		FREGSEL_LATCH_OE = 1;		
		DIPCTRL = 2'b00;							
	end
	3'b010:
	begin
		FPGA_RESET = CPU_RST; 
		FPGA_CLK = EXT_CLK;		
		FPGA2RAM_DATA_EN = 0;
		FPGA2RAM_ADDR_EN = 0;						
		if (FPGA_RD==0 && FPGA_WR==1)
		begin
			RAM_OE = 0;
			RAM_WR = 1;
			RAM_EN = 0;						
		end
		else if (FPGA_RD==1 && FPGA_WR==0)
		begin
			RAM_OE = 1;		
			RAM_WR = 0;
			RAM_EN = 0;			
		end		
		else if (FPGA_RD==1 && FPGA_WR==1)
		begin
			RAM_OE = 1;				
			RAM_WR = 1;
			RAM_EN = 4'b1111;			
		end				
		else
		begin
			RAM_OE = 1;
			RAM_WR = 1;			
			RAM_EN = 0;
		end
		RAM_ADDR_LATCH_OE = 1;	
		MCU_SEL = 12'b111111111111;			
		FREGSEL_LATCH_OE = 1;				
		DIPCTRL = 2'b00;					
	end
	3'b011:
	begin
		FPGA_RESET = MCU_RST_CTRL; 
		FPGA_CLK = MCU_CLK;		
		FPGA2RAM_DATA_EN = 1;						
		FPGA2RAM_ADDR_EN = 1;	
		RAM_OE = 1;			
		RAM_WR = 1;		
		RAM_EN = 4'b1111;		
		MCU_SEL = MCU_CODE;		
		FREGSEL_LATCH_OE = 0;				
		DIPCTRL = 2'b11;					
	end
	3'b100:
	begin
		FPGA_RESET = MCU_RST_CTRL; 
		FPGA_CLK = MCU_CLK;	
		FPGA2RAM_DATA_EN = 1;	
		FPGA2RAM_ADDR_EN = 1;										
		if (MCU_RD==0 && MCU_WR==1)
		begin
			RAM_OE = 0;
			RAM_WR = 1;
		end
		else if (MCU_RD==1 && MCU_WR==0)
		begin
			RAM_OE = 1;
			RAM_WR = 0;
		end	
		else
		begin
			RAM_OE = 1;
			RAM_WR = 1;
		end		
		RAM_EN = RAM_DATA_SEL;	
		RAM_ADDR_LATCH_OE = 0;		
		MCU_SEL = MCU_CODE;	
		FREGSEL_LATCH_OE = 0;							
		DIPCTRL = 2'b11;					
	end	
	default :	
	begin
		FPGA_RESET = MCU_RST_CTRL; 	
		FPGA_CLK = MCU_CLK;		
		FPGA2RAM_DATA_EN = 1;
		FPGA2RAM_ADDR_EN = 1;				
		RAM_OE = 1;		
		RAM_WR = 1;	
		RAM_EN = 4'b1111;	
		RAM_ADDR_LATCH_OE = 1;		
		MCU_SEL = 12'b111111111111;					
		FREGSEL_LATCH_OE = 1;				
		DIPCTRL = 2'b11;					
	end
endcase
end	

always @(*)
begin
		if (FPGA_RD==1 && FPGA_WR==0)
		begin
			FPGA2RAM_DATA_DIR = 1;
		end
		else
		begin
			FPGA2RAM_DATA_DIR = 0;
		end
end

always @(*)
begin
		if (MCU_RD==0 && MCU_WR==1)
		begin
			RAM_DATA_DIR = 0;
		end
		else
		begin
			RAM_DATA_DIR = 1;
		end
end

endmodule