?? icpld.tan.rpt
字號:
Classic Timing Analyzer report for icpld
Tue Mar 04 16:29:36 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+----------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------------+------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 18.400 ns ; SWITCH_MODE[2] ; MCU_SEL[0] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+----------------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM3256AQC208-10 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-----------------+-------------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-----------------+-------------------+
; N/A ; None ; 18.400 ns ; SWITCH_MODE[1] ; MCU_SEL[9] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[0] ; MCU_SEL[9] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[1] ; MCU_SEL[7] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[0] ; MCU_SEL[7] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[1] ; MCU_SEL[4] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[0] ; MCU_SEL[4] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[1] ; MCU_SEL[0] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[0] ; MCU_SEL[0] ;
; N/A ; None ; 18.400 ns ; SWITCH_MODE[2] ; MCU_SEL[0] ;
; N/A ; None ; 17.800 ns ; SWITCH_MODE[2] ; MCU_SEL[9] ;
; N/A ; None ; 17.800 ns ; SWITCH_MODE[2] ; MCU_SEL[7] ;
; N/A ; None ; 17.800 ns ; SWITCH_MODE[2] ; MCU_SEL[4] ;
; N/A ; None ; 17.200 ns ; MCU_CODE[0] ; MCU_SEL[0] ;
; N/A ; None ; 11.800 ns ; SWITCH_MODE[1] ; RAM_ADDR_LATCH_OE ;
; N/A ; None ; 11.800 ns ; SWITCH_MODE[0] ; RAM_ADDR_LATCH_OE ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[2] ; RAM_ADDR_LATCH_OE ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[11] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[11] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[10] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[10] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[8] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[8] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[6] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[6] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[5] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[5] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[3] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[3] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[2] ; MCU_SEL[3] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[2] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[2] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[2] ; MCU_SEL[2] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[1] ; MCU_SEL[1] ;
; N/A ; None ; 11.200 ns ; SWITCH_MODE[0] ; MCU_SEL[1] ;
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