Note this patch requires misc2.patchdiff -Naur -x CVS linux26-cvs.perforce/arch/mips/au1000/db1x00/board_setup.c i2c/arch/mips/au1000/db1x00/board_setup.c--- linux26-cvs.perforce/arch/mips/au1000/db1x00/board_setup.c	2005-05-16 11:41:54.000000000 -0500+++ i2c/arch/mips/au1000/db1x00/board_setup.c	2005-05-16 15:55:33.000000000 -0500@@ -77,6 +77,43 @@ #endif 	au_writel(0, 0xAE000010); /* turn off pcmcia power */ +#if defined(CONFIG_I2C_AU1550) && defined(CONFIG_MIPS_DB1200)+	{+	u32 freq0, clksrc;++	/* Select SMBUS in CPLD */+	bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);++	pin_func = au_readl(SYS_PINFUNC);+	au_sync();+	pin_func &= ~(3<<17 | 1<<4);+	/* Set GPIOs correctly */+	pin_func |= 2<<17;+	au_writel(pin_func, SYS_PINFUNC);+	au_sync();++	/* The i2c driver depends on 50Mhz clock */+	freq0 = au_readl(SYS_FREQCTRL0);+	au_sync();+	freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);+	freq0 |= (3<<SYS_FC_FRDIV1_BIT);+	/* 396Mhz / (3+1)*2 == 49.5Mhz */+	au_writel(freq0, SYS_FREQCTRL0);+	au_sync();+	freq0 |= SYS_FC_FE1;+	au_writel(freq0, SYS_FREQCTRL0);+	au_sync();++	clksrc = au_readl(SYS_CLKSRC);+	au_sync();+	clksrc &= ~0x01f00000;+	/* bit 22 is EXTCLK0 for PSC0 */+	clksrc |= (0x3 << 22);+	au_writel(clksrc, SYS_CLKSRC);+	au_sync();+	}+#endif+ #ifdef CONFIG_MIPS_MIRAGE 	/* enable GPIO[31:0] inputs */ 	au_writel(0, SYS_PININPUTEN);diff -Naur -x CVS linux26-cvs.perforce/drivers/i2c/busses/i2c-au1550.c i2c/drivers/i2c/busses/i2c-au1550.c--- linux26-cvs.perforce/drivers/i2c/busses/i2c-au1550.c	2005-05-16 11:41:37.000000000 -0500+++ i2c/drivers/i2c/busses/i2c-au1550.c	2005-05-16 16:16:03.000000000 -0500@@ -36,7 +36,15 @@ #include <linux/i2c.h>  #include <asm/mach-au1x00/au1000.h>-#include <asm/mach-pb1x00/pb1550.h>+#if defined(CONFIG_MIPS_PB1550)+ #include <asm/mach-pb1x00/pb1550.h>+#endif+#if defined(CONFIG_MIPS_PB1200)+ #include <asm/mach-pb1x00/pb1200.h>+#endif+#if defined(CONFIG_MIPS_DB1200)+ #include <asm/mach-db1x00/db1200.h>+#endif #include <asm/mach-au1x00/au1xxx_psc.h>  #include "i2c-au1550.h"@@ -110,22 +118,31 @@ }  static int-do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd)+do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int master_start) { 	volatile psc_smb_t	*sp; 	u32			stat;  	sp = (volatile psc_smb_t *)(adap->psc_base); -	/* Reset the FIFOs, clear events.-	*/-	sp->psc_smbpcr = PSC_SMBPCR_DC;-	sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;-	au_sync();-	do {-		stat = sp->psc_smbpcr;+	if (master_start) {+		/* Reset the FIFOs, clear events.+		*/+		stat = sp->psc_smbstat;+		sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; 		au_sync();-	} while ((stat & PSC_SMBPCR_DC) != 0);+	+		if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE))+		{+			sp->psc_smbpcr = PSC_SMBPCR_DC;+			au_sync();+			do {+				stat = sp->psc_smbpcr;+				au_sync();+			} while ((stat & PSC_SMBPCR_DC) != 0);+			udelay(50);+		}+	}  	/* Write out the i2c chip address and specify operation 	*/@@ -137,8 +154,10 @@ 	*/ 	sp->psc_smbtxrx = addr; 	au_sync();-	sp->psc_smbpcr = PSC_SMBPCR_MS;-	au_sync();+	if (master_start) {+		sp->psc_smbpcr = PSC_SMBPCR_MS;+		au_sync();+	} 	if (wait_ack(adap)) 		return -EIO; 	return 0;@@ -178,7 +197,7 @@  static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,-		    unsigned int len)+		    unsigned int len, int stop) { 	int	i; 	u32	data;@@ -205,12 +224,22 @@ 		i++; 	} -	/* The last byte has to indicate transfer done.-	*/-	sp->psc_smbtxrx = PSC_SMBTXRX_STP;+	/* The last byte has to indicate transfer done or issue a restart+	 * condition.+	 */+	if (stop)+		sp->psc_smbtxrx = PSC_SMBTXRX_STP;+	else +		sp->psc_smbtxrx = PSC_SMBTXRX_RSR; 	au_sync();-	if (wait_master_done(adap))-		return -EIO;+	if (stop) {+		if (wait_master_done(adap))+			return -EIO;+	}+	else {+		if (wait_ack(adap))+			return -EIO;+	}  	data = sp->psc_smbtxrx; 	au_sync();@@ -220,7 +249,7 @@  static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,-		     unsigned int len)+		     unsigned int len, int stop) { 	int	i; 	u32	data;@@ -241,14 +270,25 @@ 		i++; 	} -	/* The last byte has to indicate transfer done.-	*/+	/* The last byte has to indicate transfer done or issue a restart+	 * condition.+	 */ 	data = buf[i];-	data |= PSC_SMBTXRX_STP;+	if (stop)+		data |= PSC_SMBTXRX_STP;+	else+		data |= PSC_SMBTXRX_RSR;+	 	sp->psc_smbtxrx = data; 	au_sync();-	if (wait_master_done(adap))-		return -EIO;+	if (stop) {+		if (wait_master_done(adap))+			return -EIO;+	}+	else {+		if (wait_ack(adap))+			return -EIO;+	} 	return 0; } @@ -257,17 +297,22 @@ { 	struct i2c_au1550_data *adap = i2c_adap->algo_data; 	struct i2c_msg *p;-	int i, err = 0;+	int i, err = 0, ms = 1;  	for (i = 0; !err && i < num; i++) { 		p = &msgs[i];-		err = do_address(adap, p->addr, p->flags & I2C_M_RD);-		if (err || !p->len)+		err = do_address(adap, p->addr, p->flags & I2C_M_RD, ms);+		/* Only the last transfer will be finished with a stop condition +		*/+		ms = (i < num - 1) ? 0 : 1;+		if (err || !p->len) {+			ms = 1; 			continue;-		if (p->flags & I2C_M_RD)-			err = i2c_read(adap, p->buf, p->len);+		}+		if (p->flags & I2C_M_RD) +			err = i2c_read(adap, p->buf, p->len, ms); 		else-			err = i2c_write(adap, p->buf, p->len);+			err = i2c_write(adap, p->buf, p->len, ms); 	}  	/* Return the number of messages processed, or the error code.@@ -370,7 +415,7 @@ 	SMBUS_PSC_BASE, 200, 200 }; -static struct i2c_adapter pb1550_board_adapter = {+struct i2c_adapter pb1550_board_adapter = { 	name:              "pb1550 adapter", 	id:                I2C_HW_AU1550_PSC, 	algo:              NULL,@@ -378,6 +423,8 @@ 	client_register:   pb1550_reg, 	client_unregister: pb1550_unreg, };++EXPORT_SYMBOL(pb1550_board_adapter);  /* BIG hack to support the control interface on the Wolfson WM8731  * audio codec on the Pb1550 board.  We get an address and two datadiff -Naur -x CVS linux26-cvs.perforce/drivers/i2c/busses/Kconfig i2c/drivers/i2c/busses/Kconfig--- linux26-cvs.perforce/drivers/i2c/busses/Kconfig	2005-05-16 11:41:37.000000000 -0500+++ i2c/drivers/i2c/busses/Kconfig	2005-05-16 15:57:19.000000000 -0500@@ -76,7 +76,7 @@  config I2C_AU1550 	tristate "Au1550 SMBus interface"-	depends on I2C && SOC_AU1550+	depends on I2C && (SOC_AU1550 || SOC_AU1200) 	help 	  If you say yes to this option, support will be included for the 	  Au1550 SMBus interface.