/*Physical addresses of FPGA1 registers by Xue, Zhenwu*/


/*FPGA1 registers for audio codec, Physical address*/
#define PA_FPGA1_DIVIDER                0x09000000
#define PA_PLL1700_SET_REG              0x09000004
#define PA_PCM3006_SET_REG              0x09000008
#define PA_AUDIO_MOD_SWITCH             0x0900000C
#define PA_AUDIO_MOD_STATE              0x09000010

/*FPGA1 registers for DSP1/DSP2, Physical address*/
#define PA_ADSP_CNTL                    0x09000C00
#define PA_ADSP_VPORT_CNTL              0x09000C04
#define PA_ADSP_MCBSP_CNTL              0x09000C08
#define PA_BDSP_CNTL                    0x09001000
#define PA_BDSP_VPORT_CNTL              0x09001004
#define PA_BDSP_MCBSP_CNTL              0x09001008

/*ioctl commands for audio codec*/
#define SET_FPGA1_DIVIDER            0
#define SET_PLL1700_SET_REG          1
#define SET_PCM3006_SET_REG          2
#define SET_AUDIO_MOD_SWITCH         3
#define GET_AUDIO_MOD_STATE          4

/*ioctl commands for DSP1/DSP2*/
#define SET_ADSP_CNTL                5
#define SET_ADSP_VPORT_CNTL          6
#define SET_ADSP_MCBSP_CNTL          7
#define SET_BDSP_CNTL                8
#define SET_BDSP_VPORT_CNTL          9
#define SET_BDSP_MCBSP_CNTL          10

/*FPGA1 registers for audio codec, Virtual address*/
static unsigned long * VA_FPGA1_DIVIDER;
static unsigned long * VA_PLL1700_SET_REG;
static unsigned long * VA_PCM3006_SET_REG;
static unsigned long * VA_AUDIO_MOD_SWITCH;
static unsigned long * VA_AUDIO_MOD_STATE;

/*FPGA1 registers for DSP1/DSP2, Virtual address*/
static unsigned long * VA_ADSP_CNTL;
static unsigned long * VA_ADSP_VPORT_CNTL;
static unsigned long * VA_ADSP_MCBSP_CNTL;
static unsigned long * VA_BDSP_CNTL;
static unsigned long * VA_BDSP_VPORT_CNTL;
static unsigned long * VA_BDSP_MCBSP_CNTL;