#include <unistd.h>      
#include <fcntl.h>       
#include <sys/types.h>
#include <sys/stat.h>
#include <stdio.h>       
#include <linux/ioctl.h>
#include <asm-arm/ioctl.h>
#include <sys/ioctl.h>
#include <linux/kernel.h>
#include <linux/config.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include "fpga1_drv.h"

int main(){
  int FPGA1;
  int ret;
  unsigned long buf[2];

  FPGA1 = open("/dev/fpga1", O_RDWR);
  if(FPGA1<0){
    printf("Error: Unable to open device fpga1!\n");
    return -1;
  }else{
    printf("Info: Succed to open device fpga1\n");
  }
 
  buf[0] = 0x01ABCDEF;
  ret = ioctl(FPGA1, SET_FPGA1_DIVIDER, buf);
  if(ret<0){
    printf("Error: Unable to set fpga1 divider!\n");
  }
 
  buf[0] = 0x01ABCDEF;
  ret = ioctl(FPGA1, SET_PLL1700_SET_REG, buf);
  if(ret<0){
    printf("Error: Unable to set pll1700!\n");
  }
 
  buf[0] = 0x13572468;
  ret = ioctl(FPGA1, SET_PCM3006_SET_REG, buf);
  if(ret<0){
    printf("Error: Unable to set pcm3006!\n");
  }

  buf[0] = 0x01234567;
  ret = ioctl(FPGA1, SET_AUDIO_MOD_SWITCH, buf);
  if(ret<0){
    printf("Error: Unable to set audio mode!\n");
  }

  buf[0] = ioctl(FPGA1, GET_AUDIO_MOD_STATE, buf);
  printf("Current audio mode is 0x%08X\n", buf[0]);

  buf[0] = 0x14572356;
  ret = ioctl(FPGA1, SET_ADSP_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set ADSP_CNTL!\n");
  }

  buf[0] = 0x32165489;
  ret = ioctl(FPGA1, SET_ADSP_VPORT_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set ADSP_VPORT_CNTL!\n");
  }

  buf[0] = 0x40215321;
  ret = ioctl(FPGA1, SET_ADSP_MCBSP_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set ADSP_MCBSP_CNTL!\n");
  }

  buf[0] = 0x34572356;
  ret = ioctl(FPGA1, SET_BDSP_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set BDSP_CNTL!\n");
  }

  buf[0] = 0x22165489;
  ret = ioctl(FPGA1, SET_BDSP_VPORT_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set BDSP_VPORT_CNTL!\n");
  }

  buf[0] = 0x00215321;
  ret = ioctl(FPGA1, SET_BDSP_MCBSP_CNTL, buf);
  if(ret<0){
    printf("Error: Unable to set BDSP_MCBSP_CNTL!\n");
  }
 
  close(FPGA1);

  return 0;
}