/* linux/arch/arm/mach-bast/dma.c * * (c) 2003-2005 Simtec Electronics *	Ben Dooks <ben@simtec.co.uk> * * S3C2410 DMA core * * http://www.simtec.co.uk/products/EB2410ITX/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Changelog: *  27-Feb-2005 BJD  Added kmem cache for dma descriptors *  18-Nov-2004 BJD  Removed error for loading onto stopped channel *  10-Nov-2004 BJD  Ensure all external symbols exported for modules *  10-Nov-2004 BJD  Use sys_device and sysdev_class for power management *  08-Aug-2004 BJD  Apply rmk's suggestions *  21-Jul-2004 BJD  Ported to linux 2.6 *  12-Jul-2004 BJD  Finished re-write and change of API *  06-Jul-2004 BJD  Rewrote dma code to try and cope with various problems *  23-May-2003 BJD  Created file *  19-Aug-2003 BJD  Cleanup, header fix, added URL * * This file is based on the Sangwook Lee/Samsung patches, re-written due * to various ommisions from the code (such as flexible dma configuration) * for use with the BAST system board. * * The re-write is pretty much complete, and should be good enough for any * possible DMA function */#include <linux/config.h>#ifdef CONFIG_S3C2410_DMA_DEBUG#define DEBUG#endif#include <linux/module.h>#include <linux/init.h>#include <linux/sched.h>#include <linux/spinlock.h>#include <linux/interrupt.h>#include <linux/sysdev.h>#include <linux/slab.h>#include <linux/errno.h>#include <linux/delay.h>#include <asm/system.h>#include <asm/irq.h>#include <asm/hardware.h>#include <asm/io.h>#include <asm/dma.h>#include <asm/mach/dma.h>#include <asm/arch/map.h>/* io map for dma */static void __iomem *dma_base;static kmem_cache_t *dma_kmem;/* dma channel state information */s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];/* debugging functions */#define BUF_MAGIC (0xcafebabe)#define dmawarn(fmt...) printk(KERN_DEBUG fmt)#define dma_regaddr(chan, reg) ((chan)->regs + (reg))#if 1#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))#elsestatic inline voiddma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val){	pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);	writel(val, dma_regaddr(chan, reg));}#endif#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))/* captured register state for debug */struct s3c2410_dma_regstate {	unsigned long         dcsrc;	unsigned long         disrc;	unsigned long         dstat;	unsigned long         dcon;	unsigned long         dmsktrig;};#ifdef CONFIG_S3C2410_DMA_DEBUG/* dmadbg_showregs * * simple debug routine to print the current state of the dma registers*/static voiddmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs){	regs->dcsrc    = dma_rdreg(chan, S3C2410_DMA_DCSRC);	regs->disrc    = dma_rdreg(chan, S3C2410_DMA_DISRC);	regs->dstat    = dma_rdreg(chan, S3C2410_DMA_DSTAT);	regs->dcon     = dma_rdreg(chan, S3C2410_DMA_DCON);	regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);}static voiddmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan,		 struct s3c2410_dma_regstate *regs){	printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",	       chan->number, fname, line,	       regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,	       regs->dcon);}static voiddmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan){	struct s3c2410_dma_regstate state;	dmadbg_capture(chan, &state);	printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",	       chan->number, fname, line, chan->load_state,	       chan->curr, chan->next, chan->end);	dmadbg_showregs(fname, line, chan, &state);}#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))#else#define dbg_showregs(chan) do { } while(0)#define dbg_showchan(chan) do { } while(0)#endif /* CONFIG_S3C2410_DMA_DEBUG */#define check_channel(chan) \  do { if ((chan) >= S3C2410_DMA_CHANNELS) { \    printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \    return -EINVAL; \  } } while(0)/* s3c2410_dma_stats_timeout * * Update DMA stats from timeout info*/static voids3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val){	if (stats == NULL)		return;	if (val > stats->timeout_longest)		stats->timeout_longest = val;	if (val < stats->timeout_shortest)		stats->timeout_shortest = val;	stats->timeout_avg += val;}/* s3c2410_dma_waitforload * * wait for the DMA engine to load a buffer, and update the state accordingly*/static ints3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line){	int timeout = chan->load_timeout;	int took;	if (chan->load_state != S3C2410_DMALOAD_1LOADED) {		printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);		return 0;	}	if (chan->stats != NULL)		chan->stats->loads++;	while (--timeout > 0) {		if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {			took = chan->load_timeout - timeout;			s3c2410_dma_stats_timeout(chan->stats, took);			switch (chan->load_state) {			case S3C2410_DMALOAD_1LOADED:				chan->load_state = S3C2410_DMALOAD_1RUNNING;				break;			default:				printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);			}			return 1;		}	}	if (chan->stats != NULL) {		chan->stats->timeout_failed++;	}	return 0;}/* s3c2410_dma_loadbuffer * * load a buffer, and update the channel state*/static inline ints3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan,		       s3c2410_dma_buf_t *buf){	unsigned long reload;	pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",		 buf, (unsigned long)buf->data, buf->size);	if (buf == NULL) {		dmawarn("buffer is NULL\n");		return -EINVAL;	}	/* check the state of the channel before we do anything */	if (chan->load_state == S3C2410_DMALOAD_1LOADED) {		dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");	}	if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {		dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");	}	/* it would seem sensible if we are the last buffer to not bother	 * with the auto-reload bit, so that the DMA engine will not try	 * and load another transfer after this one has finished...	 */	if (chan->load_state == S3C2410_DMALOAD_NONE) {		pr_debug("load_state is none, checking for noreload (next=%p)\n",			 buf->next);		reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;	} else {		pr_debug("load_state is %d => autoreload\n", chan->load_state);		reload = S3C2410_DCON_AUTORELOAD;	}	writel(buf->data, chan->addr_reg);	dma_wrreg(chan, S3C2410_DMA_DCON,		  chan->dcon | reload | (buf->size/chan->xfer_unit));	chan->next = buf->next;	/* update the state of the channel */	switch (chan->load_state) {	case S3C2410_DMALOAD_NONE:		chan->load_state = S3C2410_DMALOAD_1LOADED;		break;	case S3C2410_DMALOAD_1RUNNING:		chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;		break;	default:		dmawarn("dmaload: unknown state %d in loadbuffer\n",			chan->load_state);		break;	}	return 0;}/* s3c2410_dma_call_op * * small routine to call the op routine with the given op if it has been * registered*/static voids3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op){	if (chan->op_fn != NULL) {		(chan->op_fn)(chan, op);	}}/* s3c2410_dma_buffdone * * small wrapper to check if callback routine needs to be called, and * if so, call it*/static inline voids3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf,		     s3c2410_dma_buffresult_t result){	pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",		 chan->callback_fn, buf, buf->id, buf->size, result);	if (chan->callback_fn != NULL) {		(chan->callback_fn)(chan, buf->id, buf->size, result);	}}/* s3c2410_dma_start * * start a dma channel going*/static int s3c2410_dma_start(s3c2410_dma_chan_t *chan){	unsigned long tmp;	unsigned long flags;	pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);	local_irq_save(flags);	if (chan->state == S3C2410_DMA_RUNNING) {		pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);		local_irq_restore(flags);		return 0;	}	chan->state = S3C2410_DMA_RUNNING;	/* check wether there is anything to load, and if not, see	 * if we can find anything to load	 */	if (chan->load_state == S3C2410_DMALOAD_NONE) {		if (chan->next == NULL) {			printk(KERN_ERR "dma%d: channel has nothing loaded\n",			       chan->number);			chan->state = S3C2410_DMA_IDLE;			local_irq_restore(flags);			return -EINVAL;		}		s3c2410_dma_loadbuffer(chan, chan->next);	}	dbg_showchan(chan);	/* enable the channel */	if (!chan->irq_enabled) {		enable_irq(chan->irq);		chan->irq_enabled = 1;	}	/* start the channel going */	tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);	tmp &= ~S3C2410_DMASKTRIG_STOP;	tmp |= S3C2410_DMASKTRIG_ON;	dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);	pr_debug("wrote %08lx to DMASKTRIG\n", tmp);#if 0	/* the dma buffer loads should take care of clearing the AUTO	 * reloading feature */	tmp = dma_rdreg(chan, S3C2410_DMA_DCON);	tmp &= ~S3C2410_DCON_NORELOAD;	dma_wrreg(chan, S3C2410_DMA_DCON, tmp);#endif	s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);	dbg_showchan(chan);	local_irq_restore(flags);	return 0;}/* s3c2410_dma_canload * * work out if we can queue another buffer into the DMA engine*/static ints3c2410_dma_canload(s3c2410_dma_chan_t *chan){	if (chan->load_state == S3C2410_DMALOAD_NONE ||	    chan->load_state == S3C2410_DMALOAD_1RUNNING)		return 1;	return 0;}/* s3c2410_dma_enqueue * * queue an given buffer for dma transfer. * * id         the device driver's id information for this buffer * data       the physical address of the buffer data * size       the size of the buffer in bytes * * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART * is checked, and if set, the channel is started. If this flag isn't set, * then an error will be returned. * * It is possible to queue more than one DMA buffer onto a channel at * once, and the code will deal with the re-loading of the next buffer * when necessary.*/int s3c2410_dma_enqueue(unsigned int channel, void *id,			dma_addr_t data, int size){	s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];	s3c2410_dma_buf_t *buf;	unsigned long flags;	check_channel(channel);	pr_debug("%s: id=%p, data=%08x, size=%d\n",		 __FUNCTION__, id, (unsigned int)data, size);	buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);	if (buf == NULL) {		pr_debug("%s: out of memory (%ld alloc)\n",			 __FUNCTION__, sizeof(*buf));		return -ENOMEM;	}	pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);	//dbg_showchan(chan);	buf->next  = NULL;	buf->data  = buf->ptr = data;	buf->size  = size;	buf->id    = id;	buf->magic = BUF_MAGIC;	local_irq_save(flags);	if (chan->curr == NULL) {		/* we've got nothing loaded... */		pr_debug("%s: buffer %p queued onto empty channel\n",			 __FUNCTION__, buf);		chan->curr = buf;		chan->end  = buf;		chan->next = NULL;	} else {		pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",			 chan->number, __FUNCTION__, buf);		if (chan->end == NULL)			pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",				 chan->number, __FUNCTION__, chan);		chan->end->next = buf;		chan->end = buf;	}	/* if necessary, update the next buffer field */	if (chan->next == NULL)		chan->next = buf;	/* check to see if we can load a buffer */	if (chan->state == S3C2410_DMA_RUNNING) {		if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {			if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {				printk(KERN_ERR "dma%d: loadbuffer:"				       "timeout loading buffer\n",				       chan->number);				dbg_showchan(chan);				local_irq_restore(flags);				return -EINVAL;			}		}		while (s3c2410_dma_canload(chan) && chan->next != NULL) {			s3c2410_dma_loadbuffer(chan, chan->next);		}	} else if (chan->state == S3C2410_DMA_IDLE) {		if (chan->flags & S3C2410_DMAF_AUTOSTART) {			s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);		}	}	local_irq_restore(flags);	return 0;}EXPORT_SYMBOL(s3c2410_dma_enqueue);static inline voids3c2410_dma_freebuf(s3c2410_dma_buf_t *buf){	int magicok = (buf->magic == BUF_MAGIC);	buf->magic = -1;	if (magicok) {		kmem_cache_free(dma_kmem, buf);	} else {		printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);	}}/* s3c2410_dma_lastxfer * * called when the system is out of buffers, to ensure that the channel * is prepared for shutdown.*/static inline voids3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan){	pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",		 chan->number, chan->load_state);	switch (chan->load_state) {	case S3C2410_DMALOAD_NONE:		break;	case S3C2410_DMALOAD_1LOADED:		if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {				/* flag error? */			printk(KERN_ERR "dma%d: timeout waiting for load\n",			       chan->number);			return;		}		break;	default:		pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",			 chan->number, chan->load_state);		return;	}	/* hopefully this'll shut the damned thing up after the transfer... */	dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);}#define dmadbg2(x...)static irqreturn_ts3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs){	s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw;	s3c2410_dma_buf_t  *buf;	buf = chan->curr;	dbg_showchan(chan);	/* modify the channel state */	switch (chan->load_state) {	case S3C2410_DMALOAD_1RUNNING:		/* TODO - if we are running only one buffer, we probably		 * want to reload here, and then worry about the buffer		 * callback */		chan->load_state = S3C2410_DMALOAD_NONE;		break;	case S3C2410_DMALOAD_1LOADED:		/* iirc, we should go back to NONE loaded here, we		 * had a buffer, and it was never verified as being		 * loaded.		 */		chan->load_state = S3C2410_DMALOAD_NONE;		break;	case S3C2410_DMALOAD_1LOADED_1RUNNING:		/* we'll worry about checking to see if another buffer is		 * ready after we've called back the owner. This should		 * ensure we do not wait around too long for the DMA		 * engine to start the next transfer		 */		chan->load_state = S3C2410_DMALOAD_1LOADED;		break;	case S3C2410_DMALOAD_NONE:		printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",		       chan->number);		break;	default:		printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",		       chan->number, chan->load_state);