library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity CM12864 is
Port(CLK:in std_logic;
	Reset:in std_logic;
	LCD_RW:out std_logic;    --out
	LCD_DI:out std_logic;    --out
	LCD_EN:out std_logic;    --out
	CS1:out std_logic;   --out
	CS2:out std_logic;   --out
	--LED:out std_logic;
	LCD_DATA:out std_logic_vector(7 downto 0));
end CM12864;




architecture Behavioral of CM12864 is 

type state is (set_dcb1,set_dcb2,init_x1,init_y1,init_z1,init_x2,init_y2,init_z2,set_ddram1,set_ddram2);
signal Current_State:state;

type ram1 is array(0 to 8) of std_logic_vector(7 downto 0);
constant
cgram1:ram1:=(x"00",x"00",x"42",x"7F",x"40",x"00",x"00",x"00",x"ff");		    --000H,000H,042H,07FH,040H,000H,0,0	x"48",x"20",x"6c",x"6c",x"6f"

signal Clk1:std_logic:='0';		   --for what?
signal Clk_Out:std_logic:='0';
signal LCD_Clk:std_logic;
--singal m:std_logic_vector(1 downto 0)

begin

LCD_EN<=Clk_Out;		 --EN 下降沿鎖存
LCD_RW<='0';



process(CLK)
variable n1:integer range 0 to 39999;
begin
	if rising_edge(CLK) then
		if n1<3 then		--39999
		n1:=n1+1;
		else
		n1:=0;
		Clk_Out<= not Clk_Out;
		end if;
	end if;
end process;

LCD_Clk<=Clk_Out;

process(Clk_Out)
variable n2:integer range 0 to 499;
begin 
	if rising_edge(Clk_Out) then 
		if n2<4 then 			 --499
		n2:=n2+1;
		else 
		n2:=0;
		Clk1<=not Clk1;
		end if;
     end if;
end process;


process(LCD_Clk,Reset,Current_State)
variable cnt1:std_logic_vector(3 downto 0);
variable cnt2:std_logic_vector(2 downto 0);	  --計算8列
variable cnt3:std_logic_vector(2 downto 0);	  --計算8行

begin
  if Reset='0' then
  	Current_State<=set_dcb1;   --   init_x1;
  	cnt1:="1111";			  --???
  	LCD_DI<='0';			  --對指令數據操作
  elsif rising_edge(LCD_Clk) then
  	Current_State<=Current_State;
  	LCD_DI<='0';			  --對指令數據操作

	case Current_State is
		when set_dcb1=>	  --顯示控制開
		cnt1:="0000";
		cnt2:="000";          --計算8列
		cnt3:="000";          --計算8行
		CS2<='0';
		CS1<='1';
		LCD_DATA<="00111111";
		Current_State<=set_dcb2;

		when set_dcb2=>   
		CS1<='0';
		CS2<='1';
		LCD_DATA<="00111111";
		Current_State<=init_z1;
		
		when init_z1=>         --設置Z地址
		CS2<='0';
		CS1<='1';
		LCD_Data<="11000000";
		Current_State<=init_z2;

		when init_z2=>
		CS1<='0';
		CS2<='1';
		LCD_Data<="11000000";
		Current_State<=init_x1;

		

		when init_x1=>		   --設置X地址
		--cnt1:="0000";
		CS1<='1';
		CS2<='0';
		LCD_Data<="10111000"+cnt3;			 --X地址不能自動增加
		Current_State<=init_y1;

		when init_y1=>		   --設置Y地址
		--CS1<='1';
		LCD_Data<="01000000";
		Current_State<=init_x2;

		when init_x2=>
		CS1<='0';
		CS2<='1';
		LCD_Data<="10111000"+cnt3;
		Current_State<=init_y2;		

		when init_y2=>
		--CS2<='1';
		LCD_Data<="01000000";
		Current_State<=set_ddram1;

		

	

		when set_ddram1=>
		  CS2<='0';
		  CS1<='1';       
		  LCD_DI<='1';    
		  LCD_DATA<=cgram1(conv_integer(cnt1));
	       Current_State<=set_ddram2;

		when set_ddram2=>
		  CS1<='0';
		  CS2<='1';   
		  LCD_DI<='1';        
		  LCD_DATA<=cgram1(conv_integer(cnt1));
		  if cnt1<"1111" then 
		    cnt1:=cnt1+1;
		  else
		    cnt1:="0000";
		  end if;
		  
		  if cnt2<"111" then
		    cnt2:=cnt2+1;
		    Current_State<=set_ddram1;
    		  else
		    cnt2:="000";
		    if cnt3<"111" then
		     cnt3:=cnt3+1;
		     Current_State<=init_x1;
		    else
		     cnt3:="000";
			Current_State<=init_x1;
 		    end if;
		  end if;
		  
	
		  

	       	   
	
		when others=>null;

	end case;
  end if;
end process;

end Behavioral;