CPLD_USER<3>          1       0     0   4     FB2_17  STD   19    I/O     O
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: nGCS0              5: nOE                9: nGCS5 
  2: CLKOUT0            6: nGCS4             10: nGCS7 
  3: CLKOUT1            7: nGCS1             11: nRSTOUT_GPA21 
  4: nGCS3              8: nGCS2            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
RESET                ..........X............................. 1       1
DATABUF_nOE          X..X.XXXXX.............................. 7       7
DATABUF_DIR          ....X................................... 1       1
BUF_nGCS0            X....................................... 1       1
CPLD_USER<5>         .X...................................... 1       1
CPLD_USER<4>         ..X..................................... 1       1
CPLD_USER<3>         ..X..................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.


assign BUF_nGCS0 = nGCS0;


assign BUF_nWE = nWE;


assign CF_nCS0 = !((!nGCS5 && !ADDR24 && !ADDR23));


assign CF_nCS1 = !((!nGCS5 && !ADDR24 && ADDR23));

FDCPE FDCPE_CPLD_USER4 (CPLD_USER[4],CLKOUT1,CLKOUT0,1'b0,1'b0);

FDCPE FDCPE_CPLD_USER3 (CPLD_USER[3],CLKOUT1,CLKOUT0,1'b0,1'b0);

FDCPE FDCPE_CPLD_USER2 (CPLD_USER[2],CLKOUT1,CLKOUT0,1'b0,1'b0);

FDCPE FDCPE_CPLD_USER1 (CPLD_USER[1],CLKOUT1,CLKOUT0,1'b0,1'b0);

FDCPE FDCPE_CPLD_USER5 (CPLD_USER[5],CLKOUT0,CLKOUT0,1'b0,1'b0);


assign CS8900_nCS = nGCS3;


assign DATABUF_DIR = nOE;


assign BUF_nOE = nOE;


assign DATABUF_nOE = (nGCS7 && nGCS5 && nGCS4 && nGCS3 && nGCS2 && nGCS1 && 
	nGCS0);


assign DM9000_nCS = nGCS4;


assign IDE_DIOR = !((!nGCS2 && !nOE && !ADDR24 && !ADDR23));


assign IDE_DIOW = !((!nGCS2 && !ADDR24 && !ADDR23 && !nWE));


assign LAN_nIOR = !((!nOE && ADDR24));


assign LAN_nIOW = !((ADDR24 && !nWE));


assign RESET = !nRSTOUT_GPA21;


assign ST16C550_CS = nGCS1;

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9536XL-5-VQ44


   -----------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 33 \
 | 1                                32 | 
 | 2                                31 | 
 | 3                                30 | 
 | 4                                29 | 
 | 5          XC9536XL-5-VQ44       28 | 
 | 6                                27 | 
 | 7                                26 | 
 | 8                                25 | 
 | 9                                24 | 
 | 10                               23 | 
 | 11                               22 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 23 /
   -----------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 nGCS0                            23 nGCS4                         
  2 LAN_nIOR                         24 TDO                           
  3 LAN_nIOW                         25 GND                           
  4 GND                              26 VCC                           
  5 CS8900_nCS                       27 nGCS1                         
  6 DM9000_nCS                       28 nGCS2                         
  7 IDE_DIOW                         29 nGCS3                         
  8 IDE_DIOR                         30 nGCS5                         
  9 TDI                              31 nGCS7                         
 10 TMS                              32 DATABUF_DIR                   
 11 TCK                              33 nRSTOUT_GPA21                 
 12 CF_nCS0                          34 ADDR24                        
 13 CF_nCS1                          35 VCC                           
 14 ST16C550_CS                      36 ADDR23                        
 15 VCC                              37 DATABUF_nOE                   
 16 CPLD_USER<1>                     38 RESET                         
 17 GND                              39 nOE                           
 18 CPLD_USER<2>                     40 nWE                           
 19 CPLD_USER<3>                     41 BUF_nOE                       
 20 CPLD_USER<4>                     42 BUF_nWE                       
 21 CPLD_USER<5>                     43 CLKOUT0                       
 22 BUF_nGCS0                        44 CLKOUT1                       


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25