module SMC_apb_if(
       
       //signal to or from APB interface
       in_Psel,
       in_Penable,
       in_Paddr,
       in_Pwrite,
       rst_preset_n_a,
       in_Pclk,
       in_Pwdata,
       out_Prdata,

       //signal to or from control register
       out_indicate,
       out_StateOfCard,
       out_TS,
       out_T,
       out_WarmEnable,                     
       out_ColdEnable,                     
       
       //signals from interrupt enable register
       out_parity_en,
       out_timeout_reset_en,
       out_timeout_character_en,
       out_timeout_block_en,
       out_empty_en,
           out_overrun_en,
       out_dataValid_en,
        
        
       //signals to conform interrupt status register
       in_parity_status,
       in_timeout_reset_status,
       in_timeout_character_status,
       in_timeout_block_status,
       in_empty_status,
       in_OverrunError_status,
       in_dataValid_status,         

       //signals to or from basic time unit register
       out_F,
       out_D, 
       
       //signals to or from character transfer time register
       out_WI,
       out_N,
 
         
       //signals to or from block transfer time register  
       out_BGT,
       out_BWI,
       out_CWI,
         
       //signal to block transfer length register
       out_BlockLength,
           
       //signal to or from tx_FIFO
       out_tx_data,
       out_txFIFO_write,                   
       
       //signal to or from rx_FIFO  
       out_rxFIFO_read,                        
       in_rx_data,
       out_ReadStatusRegister,

           clk_div
           );
       
       //signal to or from APB interface
       input in_Pclk; 
       input rst_preset_n_a;            
       input in_Psel;
       input in_Penable;
       input in_Pwrite;
       input [7:0] in_Paddr;

       input  [31:0] in_Pwdata;
       output [31:0] out_Prdata;
       
       //signal to or from control register
       output [1:0] out_indicate;
       output out_StateOfCard;
       output out_TS;
       output out_T;
       output out_WarmEnable;
       output out_ColdEnable;      
       
       //signals from interrupt enable register
       output out_parity_en;
       output out_timeout_reset_en;
       output out_timeout_character_en;
       output out_timeout_block_en;
       output out_empty_en;
       output out_overrun_en;
       output out_dataValid_en;

      //signals to conform interrupt status register
       input in_parity_status;
       input in_timeout_reset_status;
       input in_timeout_character_status;
       input in_timeout_block_status;
       input in_empty_status;
       input in_dataValid_status;
       input in_OverrunError_status;
        
      //signals to or from basic time unit register
       output [15:0] out_F;
       output [3:0] out_D;
        
      //signals to or from character transfer time register
        output [7:0] out_WI;
        output [7:0] out_N;
        
      //signals to or from block transfer time register  
        output [7:0] out_BGT;
        output [3:0] out_BWI;
        output [3:0] out_CWI;
        
      //signal to block transfer length register
        output [7:0] out_BlockLength;
         
      //signal to or from tx_FIFO
        output [7:0] out_tx_data;
        output out_txFIFO_write;              
        
      //signal to or from rx_FIFO  
        output out_rxFIFO_read;                  
        input [7:0] in_rx_data;
                
        output out_ReadStatusRegister;

        output clk_div;
        
        reg [31:0] out_Prdata;
      
        reg [7:0] Div;                        
        reg clk_div;
        reg [7:0] cnt_div;
        
        reg [7:0] cnt_indi;
        reg [1:0] out_indicate;
        reg [1:0] out_indicate_r;
        reg [1:0] out_indicate_q;
        
        reg out_StateOfCard;
        reg out_TS;
        reg out_T;
        
        reg [6:0] cnt;
        reg [6:0] cnt1;
        reg out_WarmEnable;
        reg WarmEnable_r;
        reg WarmEnable_q;
        
        
        reg out_ColdEnable;  
        reg ColdEnable_r;
        reg ColdEnable_q;
               
        reg [15:0] out_F;
        reg [3:0] out_D;           
 
        reg [7:0] out_WI;
        reg [7:0]out_N;
        
        reg [7:0] out_BGT;
        reg [3:0] out_BWI;
        reg [3:0] out_CWI;

        reg [7:0] out_BlockLength;
        
        reg [7:0] out_tx_data;
        
        wire out_txFIFO_write;
        reg txFIFO_write_r; 
        reg txFIFO_write_q;
        
        wire out_rxFIFO_read;
        reg rxFIFO_read_r;
        reg rxFIFO_read_q;
        
        reg out_parity_en;
        reg out_timeout_reset_en;
        reg out_timeout_character_en;
        reg out_timeout_block_en;
        reg out_empty_en;
        reg out_overrun_en;
        reg out_dataValid_en;

        reg out_ReadStatusRegister;
                 
        wire [31:0] ctrl;
        wire [31:0] etu;
        wire [31:0] int_en;
        wire [31:0] int_status ;
        wire [31:0] character_time ;
        wire [31:0] block_time ;
        wire [31:0] blocklength;
        wire [31:0] tx_FIFO_data;
        wire [31:0] rx_FIFO_data;
                           
//Divide the APB clock  even division only
  always @(posedge in_Pclk or negedge rst_preset_n_a )
    begin
      if(!rst_preset_n_a)
        begin
          cnt_div <=8'b0;
          clk_div <=1'b0;
        end
      else
        begin
          if(cnt_div == Div - 1'b1)
            begin
            cnt_div <= 8'b0;
            clk_div <= !clk_div;
            end
          else 
            cnt_div <= cnt_div+1'b1; 
        end
    end //end Divide the APB clock
    
       //=====================================
       //input logic
       //=====================================    
       always @(posedge in_Pclk or negedge rst_preset_n_a)
         begin
           if (rst_preset_n_a==0)
              begin       
               out_indicate_r <= 2'b00;
               out_StateOfCard <= 1'b0;
               out_TS <= 1'b0;
               out_T <= 1'b0;
               
               WarmEnable_r <= 1'b0;
               ColdEnable_r <= 1'b0;  
   
               Div <= 8'b0;
               
               out_F <= 16'b0;
               out_D <= 4'b0;           
    
               out_WI <= 8'b0;
               out_N <= 8'b0;
         
               out_BGT <= 8'b0;
               out_BWI <= 4'b0;
               out_CWI <= 4'b0;

               out_parity_en <= 1'b0;
               out_timeout_reset_en <= 1'b0;
               out_timeout_character_en <= 1'b0;
               out_timeout_block_en <= 1'b0;
               out_empty_en <= 1'b0;
                           out_overrun_en <= 1'b0;
               out_dataValid_en <= 1'b0;

                           
               out_BlockLength <= 8'b0;
         
               out_tx_data <= 8'b0;
               txFIFO_write_r <= 1'b0;  
               rxFIFO_read_r <= 1'b0;
              end
           else
             if ( (in_Psel==1) && (in_Penable==1) && (in_Pwrite==1))
               begin
                 case(in_Paddr)
                   `Control_r:
                   begin
                     out_indicate_r <= in_Pwdata[6:5];
                     out_StateOfCard <= in_Pwdata[4];
                     out_TS <= in_Pwdata[2];
                     out_T <= in_Pwdata[3];
                     WarmEnable_r <= in_Pwdata[1];
                     ColdEnable_r <= in_Pwdata[0]; 
                     Div <= in_Pwdata[23:16];  
                   end
                                      
                   `InterruptEnable_r:
                   begin
                     out_parity_en <= in_Pwdata[6];
                     out_timeout_reset_en <= in_Pwdata[5];
                     out_timeout_character_en <= in_Pwdata[4];
                     out_timeout_block_en <= in_Pwdata[3];
                     out_empty_en <= in_Pwdata[2];
                     out_overrun_en <= in_Pwdata[1];
                     out_dataValid_en <= in_Pwdata[0]; 
                       end
                              
                  `BasicTimeUnit_r: