//******************************************************************
//   (C) COPYRIGHT  2007  Southeast University ASIC Center
//    ALL RIGHTS RESERVED
//    File     : transmit_FIFO.v
//    Author   : Jun Yi 
//    Data     : 2007-9-20
//    Version  : 1.0
//    Abstract : transmit_FIFO
//*******************************************************************

module transmit_FIFO(
        // clock and reset
                   clk_div            ,
                   in_Pclk            ,
                   rst_preset_n_a           ,
	// fifo control signal
                   in_write          ,
                   in_TransmitRead          ,
                   out_TransmitFIFOEmpty    ,
                   //out_fifo_full     ,                      //add                        
                  // out_fifo_afull    ,                      //add 
        // fifo data           
                   in_txData     ,
                   out_txData    );
                   
  // clock and reset
  input                         in_Pclk          ;
  input                         clk_div          ;                 
  input                         rst_preset_n_a   ;                 

	// fifo control signal
  input                         in_write        ;// write fifo enable                 
  input                         in_TransmitRead  ;// read fifo enable
 // output                        out_fifo_afull  ;// fifo almost full ,assert when fifo has last 1 level to
						 // be full
  output                        out_TransmitFIFOEmpty  ;// fifo empty indication
//  output                        out_fifo_full   ;// fifo full indication

  
        // fifo data           
  output[`FIFOWIDTH -1:0]         out_txData   ;// fifo read data output
  input [`FIFOWIDTH -1:0]         in_txData    ;// fifo write data input                 
  
  reg   [`FIFOPTWIDTH -1:0]      rpointer          ;// fifo read pointer,point to data to be read out
  reg   [`FIFOPTWIDTH -1:0]      wpointer          ;// fifo write pointer ,point to data to be write in
  reg   [`FIFOWIDTH -1:0]        fifo_mem[`FIFODEPTH -1:0];// fifo register array
  wire  [`FIFOPTWIDTH -2:0]      fifo_depth        ;// fifo depth,means the number of data in the fifo  
  
  wire out_fifo_full; 
  
///***********************************************************************  
//// full ,empty , halfempty generating    ///////////////////////////////
//// overflow ,underflow  generating       ///////////////////////////////
///***********************************************************************
  // if read pointer is equal to write pointer and fifo depth is 0, fifo empty
  assign out_TransmitFIFOEmpty = (fifo_depth == 0) & (rpointer[`FIFOPTWIDTH -1]
                                    ==wpointer[`FIFOPTWIDTH -1]);
  
  // if read pointer is not equal to write pointer and fifo depth is 0, fifo full
  assign out_fifo_full = (fifo_depth == 0) & (rpointer[`FIFOPTWIDTH -1] 
                                     !=wpointer[`FIFOPTWIDTH -1]);  
  // fifo depth is write pointer minus read pointer,this is a carry borrow subtration
  assign fifo_depth = wpointer[`FIFOPTWIDTH -2:0] - rpointer[`FIFOPTWIDTH -2:0];
  // if fifo depth is n'b11..111 , it means fifo has last 1 level to be full
 // assign out_fifo_afull = &fifo_depth; // 1 data to full
  assign out_txData = fifo_mem[rpointer[`FIFOPTWIDTH -2:0]];
///*************************************************************************
///  write data ,wpointer  /////////////////////////////////////////////////
///*************************************************************************
  integer i; // index
// if  write fifo enable and fifo is not full,push the data into where 
// the write pointer point to. And then write pointer increase by 1. 
  always @ (posedge in_Pclk or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      for(i=0;i<`FIFODEPTH;i=i+1)
        fifo_mem[i] <= 0;
    else  
      if( in_write &(!out_fifo_full))
        fifo_mem[wpointer[`FIFOPTWIDTH -2:0]] <= in_txData;
          
  always @ (posedge in_Pclk or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      wpointer <= 0;
    else
      if(in_write & (!out_fifo_full))
        wpointer <= wpointer + 1;        
               
////********************************************************************
///// read data , rpointer /////////////////////////////////////////////
////********************************************************************

// fifo output data is always connected to the data read pointer point to.  
// if read fifo enable and fifo is not empty, read pointer increase by 1. 
  always @ (posedge clk_div or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      rpointer <= 0;
    else 
      if( in_TransmitRead &(!out_TransmitFIFOEmpty))
          rpointer <= rpointer + 1;
  
endmodule