#define RAVEN_MPC_MEREN_MATOM	0x2000	/* MATOI machine check enable */#define RAVEN_MPC_MEREN_DFLT	0x4000	/* Default MPC Master ID select */#define RAVEN_MPC_MEREN_VALID	0x6F2F	/* Mask for valid MEREN bits *//* Raven MPC Error Status (MERST) register bit masks */#define RAVEN_MPC_MERST_RTA	0x01	/* C PCI mstr Recvd Target Abort */#define RAVEN_MPC_MERST_SMA	0x02	/* C PCI mstr Signld Target Abort */#define RAVEN_MPC_MERST_SERR	0x04	/* C PCI System Error */#define RAVEN_MPC_MERST_PERR	0x08	/* C PCI Parity Error */#define RAVEN_MPC_MERST_MATO	0x20	/* C MPC Address Bus Time-out */#define RAVEN_MPC_MERST_OVF	0x80	/* C Error Status Overflow */#define RAVEN_MPC_MERST_VALID	0xAF	/*   Mask for valid MERST bits */#define RAVEN_MPC_MERST_CLR	0xAF	/*   Clears all errors *//* Raven PCI Configuration Status register bit masks */#define RAVEN_PCI_CFG_STATUS_FAST    0x0010  /*   Fast back-to-back capable */#define RAVEN_PCI_CFG_STATUS_DPAR    0x0100  /* C Data prity error detected */#define RAVEN_PCI_CFG_STATUS_SELTIM0 0x0200  /*   Device select timing bit 0 */#define RAVEN_PCI_CFG_STATUS_SELTIM1 0x0400  /*   Device select timing bit 1 */#define RAVEN_PCI_CFG_STATUS_SIGTA   0x0800  /* C Signalled Target Abort */#define RAVEN_PCI_CFG_STATUS_RCVTA   0x1000  /* C Received Target Abort */#define RAVEN_PCI_CFG_STATUS_RCVMA   0x2000  /* C Received Master Abort */#define RAVEN_PCI_CFG_STATUS_SIGSE   0x4000  /* C Signalled System Error */#define RAVEN_PCI_CFG_STATUS_RCVPE   0x8000  /* C Detected Parity Error */#define RAVEN_PCI_CFG_STATUS_VALID   0xFF10  /*   Valid status bits */#define RAVEN_PCI_CFG_STATUS_CLR     0xF900  /*   Clears all conditions *//* * PMC Span DEC21150 PCI-to-PCI Bridge device-specific registers * * These registers are in Configuration Space and are extensions to a * standard type 1 PCI header. */#define PCI_CFG_DEC21150_CHIP_CTRL 0x40#define PCI_CFG_DEC21150_DIAG_CTRL 0x41#define PCI_CFG_DEC21150_ARB_CTRL  0x42#define PCI_CFG_DEC21150_EVNT_DSBL 0x64#define PCI_CFG_DEC21150_GPIO_DOUT 0x65#define PCI_CFG_DEC21150_GPIO_CTRL 0x66#define PCI_CFG_DEC21150_GPIO_DIN  0x67#define PCI_CFG_DEC21150_SEC_CLK   0x68     /* secondary clock control reg */#define PCI_CFG_DEC21150_SERR_STAT 0x6A/* programmable interrupt controller (PIC) */#define PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. *//* programmable interrupt timers */#define PIT_BASE_ADR		SL82565_TMR1_CNT0	/* timeraddrs */#define PIT_REG_ADDR_INTERVAL	1#define PIT_CLOCK		1193180/* serial ports (COM1 - COM4) */#ifdef INCLUDE_I8250_SIO#define COM1_BASE_ADR		pc87303_COM1	/* serial port 1 */#define COM2_BASE_ADR		pc87303_COM2	/* serial port 2 */#define UART_REG_ADDR_INTERVAL  1       	/* addr diff of adjacent regs */#define N_UART_CHANNELS 	2		/* No. serial I/O channels */#endif /* INCLUDE_I8250_SIO */#ifdef INCLUDE_Z85230_SIO#define BAUD_CLK_FREQ		10000000        /* 10 MHz "P Clock" (fixed) */#define REG_8530_WRITE(reg,val) sysOutByte((UINT32)(reg), (UINT8)(val))#define REG_8530_READ(reg,pVal) *(UINT8 *)pVal = sysInByte((UINT32)reg)#define DATA_REG_8530_DIRECT/* #  define Z8530_RESET_DELAY_COUNT 2000 */#define Z8530_RESET_DELAY \        { \        int i; \        for (i = 0; i < Z8530_RESET_DELAY_COUNT; i++) \                ; /* do nothing */ \        }#endif /* INCLUDE_Z85230_SIO *//* total number of serial ports */#if defined(INCLUDE_I8250_SIO) && defined(INCLUDE_Z85230_SIO)#  define N_SIO_CHANNELS	4		/* No. serial I/O channels */#elif defined(INCLUDE_I8250_SIO)#  define N_SIO_CHANNELS	2		/* No. serial I/O channels */#elif defined(INCLUDE_Z85230_SIO)#  define N_SIO_CHANNELS	2		/* No. serial I/O channels */#else#  define N_SIO_CHANNELS	0		/* No. serial I/O channels */#endif/* non-volatile (battery-backed) ram defines * * the top 16 bytes are used for the RTC registers */#define	BBRAM_ADRS		0		/* base address */#define	BBRAM_SIZE		0x1ff0		/* 8k NVRAM Total Size *//* factory ethernet address */#define	BB_ENET			((char *)(BBRAM_ADRS + 0x1f2c))/* MK48TXX register settings *//* flag register */#define MK48T_FLAGS		((char *)(BBRAM_ADRS + 0x1ff0))/* alarm clock registers, 4 1byte locations */#define ALARM_CLOCK		((char *)(BBRAM_ADRS + 0x1ff2))/* interrupt register */#define MK48T_INTR		((char *)(BBRAM_ADRS + 0x1ff6))/* watchdog timer register */#define WD_TIMER		((char *)(BBRAM_ADRS + 0x1ff7))/* MK48TXX bb time of day clk, 8 1byte locations */#define	TOD_CLOCK 		((char *)(BBRAM_ADRS + 0x1ff8))#define NV_RAM_IO_MAPPED	/* nvram is io mapped in ISA space */#define NV_RAM_READ(x)		sysNvRead (x)#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)#define NV_RAM_LSB_REG		m48TXX_LSB_REG#define NV_RAM_MSB_REG		m48TXX_MSB_REG#define NV_RAM_DAT_REG		m48TXX_DAT_REG/* ncr810/ncr825 delay loop count */#define NCR810_DELAY_MULT       10/* SUPER I/O defines */#define SUPER_IO_BASE1		0x002e#define SUPER_IO_BASE2		0x015c#define SUPER_IO_KBC_BASE_ADR	0x60#define SUPER_IO_KBC_CMND_ADR	0x64#define SUPER_IO_FDC_BASEHI	0x03#define SUPER_IO_FDC_BASELO	0xf0#define SUPER_IO_COM1_BASEHI    0x03#define SUPER_IO_COM1_BASELO    0xf8#define SUPER_IO_COM2_BASEHI    0x02#define SUPER_IO_COM2_BASELO    0xf8#define SUPER_IO_PP_BASEHI      0x03#define SUPER_IO_PP_BASELO      0xbc#define SUPER_IO_FDC_PS2	0x40#define SUPER_IO_PP_CFG		0x12#define SUPER_IO_ENBL_INTS	0x02/* INTERRUPT DEFINES */#define ISA_INTERRUPT_BASE	0x00#define EXT_INTERRUPT_BASE	0x10#define TIMER_INTERRUPT_BASE	0x20#define IPI_INTERRUPT_BASE	0x24#define ERR_INTERRUPT_BASE	0x28#define ESCC_INTERRUPT_BASE	0x00/* interrupt level defines (NOTE: these are int. NUMBERS, not levels) */#ifdef INCLUDE_MPIC/* PIB (8259) interrupt connection */#define PIB_INT_LVL		( 0x00 + EXT_INTERRUPT_BASE ) /* ISA interrupt defines (NOTE: these are int. NUMBERS, not levels) */ /* programable timer interrup level */#define PIT_INT_LVL		( 0x00 + ISA_INTERRUPT_BASE )/* keyboard interrupt level ( currently not supported ) */#define KBD_INT_LVL		( 0x01 + ISA_INTERRUPT_BASE )/* com port 2 interrupt level */#define COM2_INT_LVL		( 0x03 + ISA_INTERRUPT_BASE )/* com port 1 interrupt level */#define COM1_INT_LVL		( 0x04 + ISA_INTERRUPT_BASE )/* floppy interrupt */#define FD_INT_LVL		( 0x06 + ISA_INTERRUPT_BASE )/* parallel port interrupt level */#define PP_INT_LVL		( 0x07 + ISA_INTERRUPT_BASE )/* z8536 timer interrupt level */#define Z8536_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )/* z85230 ESCC interrupt level (shared with z8536) */#define Z85230_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )/* mouse interrupt ( currently not supported ) */#define MOUSE_INT_LVL		( 0x0c + ISA_INTERRUPT_BASE ) #ifdef	INCLUDE_ATA#define	IDE_CNTRLR0_INT_LVL	( 0x0e + ISA_INTERRUPT_BASE )#define	IDE_CNTRLR1_INT_LVL	( 0x0f + ISA_INTERRUPT_BASE )#endif	/* INCLUDE_ATA *//* PCI interrupt levels */ /* Falcon-ECC error interrupt */#define ECC_INT_LVL		( 0x01 + EXT_INTERRUPT_BASE )/* ethernet interrupt level */#define LN_INT_LVL		( 0x02 + EXT_INTERRUPT_BASE )/* SCSI interrupt level */#define SCSI_INT_LVL		( 0x03 + EXT_INTERRUPT_BASE )/* Graphics interrupt level ( not currently used ) */#define GRPH_INT_LVL		( 0x04 + EXT_INTERRUPT_BASE )/* Secondary Ethernet interrupt level */#define LN2_INT_LVL		( 0x0a + EXT_INTERRUPT_BASE )/* * PMC interrupt levels * PMC_INT_LVL1 - PMC1 INTA#, PMC2 INTD# * PMC_INT_LVL2 - PMC1 INTB#, PMC2 INTC# * PMC_INT_LVL3 - PMC1 INTC#, PMC2 INTB# * PMC_INT_LVL4 - PMC1 INTD#, PMC2 INTA# */#define PMC_INT_LVL1		( 0x09 + EXT_INTERRUPT_BASE )#define PMC_INT_LVL2		( 0x0a + EXT_INTERRUPT_BASE )#define PMC_INT_LVL3		( 0x0b + EXT_INTERRUPT_BASE )#define PMC_INT_LVL4		( 0x0c + EXT_INTERRUPT_BASE )#define PCI_INT_LVL1		PMC_INT_LVL1#define PCI_INT_LVL2		PMC_INT_LVL2#define PCI_INT_LVL3		PMC_INT_LVL3#define PCI_INT_LVL4		PMC_INT_LVL4#define PCI_INT_LVL5		( 0x08 + EXT_INTERRUPT_BASE )#define PCI_INT_LVL6		( 0x05 + EXT_INTERRUPT_BASE )#define PCI_INT_LVL7		( 0x06 + EXT_INTERRUPT_BASE )#define	MAX_MPIC_INT_LVL	(EXT_INTERRUPT_BASE + 0xE)#else /* !INCLUDE_MPIC */#define PIT_INT_LVL		0x00	/* programable timer interrup level */#define KBD_INT_LVL		0x01	/* keyboard interrupt level */#define COM2_INT_LVL		0x03	/* com port 2 interrupt level */#define COM1_INT_LVL		0x04	/* com port 1 interrupt level */#define LM_SIG_INT_LVL		0x05	/* used for mailbox intr */#define FD_INT_LVL		0x06	/* floppy disk interrupt level */#define PP_INT_LVL		0x07	/* parallel port interrupt level */#define Z8536_INT_LVL		0x09	/* z8536 timer interrupt level */#define Z85230_INT_LVL		0x09	/* z85230 ESCC interrupt level */#define LN_INT_LVL		0x0a	/* ethernet interrupt level */#define SCSI_INT_LVL		0x0e	/* scsi interrupt level */#define PMC_INT_LVL1		0x0a	/* PCI INTA */#define PMC_INT_LVL2		0x0b	/* PCI INTB */#define PMC_INT_LVL3		0x0e	/* PCI INTC */#define PMC_INT_LVL4		0x0f	/* PCI INTD */#define PCI_INT_LVL1		PMC_INT_LVL1#define PCI_INT_LVL2		PMC_INT_LVL2#define PCI_INT_LVL3		PMC_INT_LVL3/* On MTXPlus, secondary PCI bus interrupts are wired together at the 8259 */#define PCI_INT_LVL4		0x0b#define PCI_INT_LVL5		0x0b#define PCI_INT_LVL6		0x0b#define PCI_INT_LVL7		0x0b#define LN2_INT_LVL		0x0f	/* ethernet interrupt level */#ifdef	INCLUDE_ATA#define IDE_CNTRLR0_INT_LVL	0x0e	/* ATA/EIDE cntrlr 0 interrupt level */#define IDE_CNTRLR1_INT_LVL	0x0f	/* ATA/EIDE cntrlr 1 interrupt level */#endif	/* INCLUDE_ATA */#endif /* INCLUDE_MPIC *//* interrupt vector definitions */#define INT_VEC_IRQ0		0x00	/* vector for IRQ0 *//* ISA interrupt vectors */#define PIT_INT_VEC		INT_VEC_IRQ0 + PIT_INT_LVL#define KBD_INT_VEC		INT_VEC_IRQ0 + KBD_INT_LVL#define PP_INT_VEC		INT_VEC_IRQ0 + PP_INT_LVL#define COM1_INT_VEC		INT_VEC_IRQ0 + COM1_INT_LVL#define COM2_INT_VEC		INT_VEC_IRQ0 + COM2_INT_LVL#define Z8536_INT_VEC		INT_VEC_IRQ0 + Z8536_INT_LVL#define Z85230_INT_VEC		INT_VEC_IRQ0 + Z85230_INT_LVL#define FD_INT_VEC		INT_VEC_IRQ0 + FD_INT_LVL/* PCI/MPIC interrupt vectors */#define LN_INT_VEC		INT_VEC_IRQ0 + LN_INT_LVL#define SCSI_INT_VEC		INT_VEC_IRQ0 + SCSI_INT_LVL#define LN2_INT_VEC		INT_VEC_IRQ0 + PMC_INT_LVL2#define SCSI_INT_VEC2		INT_VEC_IRQ0 + PMC_INT_LVL3#define PIB_INT_VEC		INT_VEC_IRQ0 + PIB_INT_LVL#define PCI_PRI_INTA_VEC	INT_VEC_IRQ0 + PMC_INT_LVL1#define PCI_PRI_INTB_VEC	INT_VEC_IRQ0 + PMC_INT_LVL2#define PCI_PRI_INTC_VEC	INT_VEC_IRQ0 + PMC_INT_LVL3#define PCI_PRI_INTD_VEC	INT_VEC_IRQ0 + PMC_INT_LVL4/* Timer Interrupt (IPI0) */#define TIMER0_INT_LVL		( 0x00 + TIMER_INTERRUPT_BASE )/* Timer interrupt vector */#define TIMER0_INT_VEC		INT_VEC_IRQ0 + TIMER0_INT_LVL/* * Address range definitions for PCI bus. * * Used with vxMemProbe() hook sysBusProbe(). */#define IS_PCI_ADDRESS(adrs)	((((UINT32)(adrs) >= \				 (UINT32)PCI_MSTR_MEMIO_LOCAL) && \				 ((UINT32)(adrs) < \				 (UINT32)(PCI_MSTR_MEMIO_LOCAL + \				 (PCI_MSTR_MEMIO_SIZE-1)))) && \				(((UINT32)(adrs) >= \				 (UINT32)ISA_MSTR_IO_LOCAL) && \				 ((UINT32)(adrs) < \				 (UINT32)(ISA_MSTR_IO_LOCAL + \				 (PCI_MSTR_IO_SIZE-1)))))#define SYS_REG_SIOP_HW_REGS    {0,0,0,0,0,1,0,0,0,0,0}/* PCI bus number for primary PCI bus */#define PCI_PRIMARY_BUS         0/* Fixed PCI-to-PCI Bridge configuration parameters */#define P2P_CLR_STATUS          0xFFFF0000#define P2P_SEC_BUS_RESET       (0x0040 << 16)#define P2P_CLK_ENABLE          0x00       /* enable clocks on all slots */#define P2P_PMC_DISABLE         0#define P2P_PMC_ENABLE          7/* * Support for determining if we're ROM based or not.  _sysInit * saves the startType parameter at location ROM_BASED_FLAG. */#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \                                     PCI_AUTOCONFIG_FLAG_OFFSET) )#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )#ifdef __cplusplus}#endif#endif /* INCmtxh */