/* * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS  * are defined in config.h, Makefile. * All definitions for these constants must be identical. */#define	ROM_SIZE		0x00100000	/* 1MB ROM space */#define ROM_BASE_ADRS		0xfff00000	/* base address of ROM */#define ROM_TEXT_ADRS		(ROM_BASE_ADRS + 0x100)/* * PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE control the * sizes of the available PCI address spaces. The windows defined by these * parameters must be large enough to accommodate all of the PCI memory and * I/O space requests found during PCI autoconfiguration. If they are not, * some devices will not be autoconfigured. * * Be aware that these values alter entries in the sysPhysMemDesc[] array * (in sysLib.c) and affect the size of the resulting MMU tables at the * rate of 128:1. For each 128K of address space, a 1K piece of RAM will be * used for MMU tables.  If the region is very large, modifications to * sysLib.c can be made to use BAT (Block Address Translation) registers * instead of MMU page tables to map the memory. * * NOTE: Since PCI auto-configuration is performed by the bootroms, *       changing any of these values requires the creation of new bootroms. */#ifndef EXTENDED_PCI    /*     * CPU Space                     PCI Space (these are the values used     *                                          for autoconfig setup)     * 0x80000000  ----------------- ISA_MSTR_IO_LOCAL     *            | ISA LEGACY      |          * 0x80004000  ----------------- ISA_MSTR_IO_LOCAL + ISA_LEGACY_SIZE     *            | PCI 16-bit I/O  |     * 0x80010000  ----------------- PCI_MSTR_IO_LOCAL = ISA Master + ISA Size     *            | PCI 32-bit I/O  |          * 0x81810000  ----------------- PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE     *            :                 :     *       * 0xC0000000  ----------------- PCI_MSTR_MEMIO_LOCAL     *            | NPREF PCI MEM   |      * 0xC0800000  ----------------- PCI_MSTR_MEM_LOCAL = MemIO local + MemIO Sz     *            | PCI 32-bit MEM  |     * 0xC1800000  ----------------- PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE     *      * the pseudo-PReP map (default) has the following maximum PCI size      * limitations:     *     * PCI_MSTR_IO_SIZE = PCI_MSTR_MEMIO_LOCAL (0xc0000000)     *                    - ISA_MSTR_IO_LOCAL  (0x80000000)     *                    - ISA_MSTR_IO_SIZE   (0x00010000)     *     * therefore: the maximum value of PCI_MSTR_IO_SIZE = 0x3fff0000     *     * PCI_MSTR_MEM_SIZE must be < (MPIC_BASE_ADRS - PCI_MSTR_MEMIO_LOCAL)     * (< 0x3B800000 - ~1G)     *     */#   define PCI_MSTR_IO_SIZE     0x00800000      /* 8MB */#   define PCI_MSTR_MEMIO_SIZE  0x00800000      /* 8MB */#   define PCI_MSTR_MEM_SIZE    0x01000000      /* 16MB (default) */#else    /*     * the Extended PCI map (optional) maximizes PCI mapped Memory space.     *     * CPU Space                     PCI Space (these are the values used     *                                          for autoconfig setup)     * 0x40000000 -----------------  PCI_MSTR_MEMIO_LOCAL     *            | NPREF PCI MEM   |     * 0x40800000  ----------------- PCI_MSTR_MEM_LOCAL = MemIO local + MemIO Sz     *            | PCI 32-bit MEM  |     *            :                 :     * 0xFC000000  ----------------- MPIC_BASE_ADRS     *            | MPIC registers  |     * 0xFD000000  ----------------- ISA_MSTR_IO_LOCAL     *            | ISA LEGACY      |     * 0xFD004000  ----------------- ISA_MSTR_IO_LOCAL + ISA_LEGACY_SIZE     *            | PCI 16-bit I/O  |     * 0xFD010000  ----------------- ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE     *            | PCI 32-bit I/O  |     * 0xFE810000  ----------------- PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE     *     * The maximum value of PCI_MSTR_IO_SIZE = MPIC_BASE_ADRS -      *                                         PCI_MSTR_MEMIO_LOCAL      * therefore: maximum value of PCI_MSTR_IO_SIZE = 0xBC000000 (~3GB)     *     */#   define PCI_MSTR_MEMIO_SIZE  0x00800000      /* 8MB */#   define PCI_MSTR_IO_SIZE     0x00800000      /* 8MB */#   define PCI_MSTR_MEM_SIZE    0x02000000      /* 32MB (default) */#endif/* Shared-memory Backplane Network parameters *//*  * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane * driver and the auto address setup which are defined in configAll.h. */#undef  INCLUDE_SM_NET#undef  INCLUDE_SM_SEQ_ADDR/* * These defines are used to initialize the External Source * Vector/Priority registers in the MPIC.  The following can * be defined: interrupt sensitivity, polarity and interrupt priority. * * Note: by default a 0 into the sense bit(22) will setup for level * sensitive, and a 0 into the polarity bit(23) will setup for low * polarity. * * At initialization all external interrupt sources are disabled * except for the 8259 input, which is enabled in the MPIC driver. * * All currently unused interrupt sources are set to a priority of * 0, which will not allow them to be enabled.  If any one of these * levels is to be used, the priority value must be changed here. */ #define INIT_EXT_SRC0           ( INT_MASK_BIT | HIGH_POLARITY | LEVEL_SENSE |\                                  PRIORITY_LVL8 )   /* PIB (8259) */ #define INIT_EXT_SRC1           ( INT_MASK_BIT | PRIORITY_LVL0 ) /* Falcon ECC*/ #define INIT_EXT_SRC2		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL14 )  /* EthernetI */ #define INIT_EXT_SRC3		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )   /* SCSI */ #define INIT_EXT_SRC4		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )  /* not used */#define INIT_EXT_SRC5		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* SPCI6 */ #define INIT_EXT_SRC6		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* SPCI7 */ #define INIT_EXT_SRC7		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* SPCI4 */ #define INIT_EXT_SRC8		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* SPCI5 */ #define INIT_EXT_SRC9		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* PCI1 */ #define INIT_EXT_SRC10		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* PCI2 */ #define INIT_EXT_SRC11		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* PCI3 */ #define INIT_EXT_SRC12		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* PCI4 */ #define INIT_EXT_SRC13		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* LM/SIG 0 */ #define INIT_EXT_SRC14		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* LM/SIG 1 */ #define INIT_EXT_SRC15		( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )  /* EthernetII */#include "mtx.h"/* Defines for sysDec21x40UpdateLoadStr */#define     PRIMARY_ENET_BUS        0x00#define     PRIMARY_ENET_DEV        0x0e#define     PRIMARY_ENET_FNC        0x00#ifdef INCLUDE_SECONDARY_ENET#   define     NUM_ENET_UNITS          2#   define     SECONDARY_ENET_BUS      0x00#   define     SECONDARY_ENET_DEV      0x13#   define     SECONDARY_ENET_FNC      0x00#else#   define     NUM_ENET_UNITS          1#endif /* INCLUDE_SECONDARY_ENET */#if FALSE	/* set TRUE to include USB support *//* USB Host Components */#   define INCLUDE_USB 			/* Main USB Component */#   undef  INCLUDE_USB_INIT		/* USB Initialization */#   undef  INCLUDE_UHCI			/* UHCI Controller Driver */#   undef  INCLUDE_UHCI_INIT    	/* UHCI Initialization */#   define INCLUDE_OHCI			/* OHCI Controller Driver */#   undef  INCLUDE_OHCI_INIT		/* OHCI Initialization */#   undef  INCLUDE_OHCI_PCI_INIT 	/* OHCI PCI Initialization */#   define INCLUDE_USBTOOL		/* usbTool Application */#   undef  INCDLUE_USB_AUDIO_DEMO	/* USB Audio Demo */#   define INCLUDE_USB_MOUSE 		/* USB Mouse Driver */#   undef  INCLUDE_USB_MOUSE_INIT 	/* Mouse Driver Initialization */#   define INCLUDE_USB_KEYBOARD 	/* USB Keyboard Driver */#   undef  INCLUDE_USB_KEYBOARD_INIT 	/* Keyboard Driver Initialization */#   define INCLUDE_USB_PRINTER 		/* USB Printer Driver */#   undef  INCLUDE_USB_PRINTER_INIT 	/* Printer Driver Initialization */#   define INCLUDE_USB_SPEAKER 		/* USB Speaker Driver */#   undef  INCLUDE_USB_SPEAKER_INIT 	/* Speaker Driver Initialization */#   undef  INCLUDE_USB_MS_BULKONLY 	/* USB Bulk Driver */#   undef  INCLUDE_USB_MS_BULKONLY_INIT /* Bulk Driver Initialization */#   undef  INCLUDE_USB_MS_CBI 		/* USB CBI Driver */#   undef  INCLUDE_USB_MS_CBI_INIT 	/* CBI Driver Initialization */#   undef  INCLUDE_USB_PEGASUS_END 	/* USB Pegasus Network Driver */#   undef  INCLUDE_USB_PEGASUS_END_INIT /* Pegaus Driver Initialization *//*  USB Parameters */#   define BULK_DRIVE_NAME "/bd" 		/* Bulk Drive Name */	#   define CBI_DRIVE_NAME "/cbid" 		/* CBI Drive Name */#   define PEGASUS_IP_ADDRESS "90.0.0.3" 	/* Pegasus IP Address */#   define PEGASUS_DESTINATION_ADDRESS "90.0.0.53" /* Pegasus Destination Address */#   define PEGASUS_NET_MASK 0xffffff00 		/* Pegasus Net Mask */#   define PEGASUS_TARGET_NAME "host" 		/* Pegasus Target Name */#endif#ifdef __cplusplus}#endif#if defined(PRJ_BUILD)#   include "prjParams.h"#endif#endif	/* INCconfigh */