/* romInit.s - Motorola MTX ROM initialization module *//* Copyright 1984-2000 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999,2000 Motorola, Inc. All Rights Reserved */	.data	.globl  copyright_wind_river	.long   copyright_wind_river/*modification history--------------------01c,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)01b,24jul00,dmw  SPR 31871, fix to dram speed selection01a,08jun99,dmw  Ported from romInit.s, 01h,15mar99,srr.*//*DESCRIPTIONThis module contains the entry code for the VxWorks bootrom.The entry point romInit, is the first code executed on power-up.It sets the BOOT_COLD parameter to be passed to the genericromStart() routine.The routine sysToMonitor() jumps to the location 4 bytespast the beginning of romInit, to perform a "warm boot".This entry point allows a parameter to be passed to romStart().This code is intended to be generic across PowerPC 603/604 boards.Hardware that requires special register setting or memorymapping to be done immediately, may do so here.*/#define	_ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "asm.h"#include "config.h"#include "regs.h"	#include "hawkI2c.h"		/* Exported internal functions */	FUNC_EXPORT(_romInit)		/* start of system code */	FUNC_EXPORT(romInit)		/* start of system code */	/* externals */	.extern	sysGetBusSpd	.extern	sysDramSpdGet#ifdef	INCLUDE_I2C	.extern	sysDimmRefreshRateGet	.extern	sysHawkDimmTypeGet#endif	/* INCLUDE_I2C */	.extern romStart	/* system initialization routine */	.text	.align 2		/******************************************************************************** romInit - entry point for VxWorks in ROM** romInit*     (*     int startType	/@ only used by 2nd entry point @/*     )*/_romInit:romInit:	bl	cold		bl	warm	/* copyright notice appears at beginning of ROM (in TEXT segment) */	.ascii   "Copyright 1984-1998 Wind River Systems, Inc."	.align 2cold:	li	r24, BOOT_COLD	bl	start		/* skip over next instruction */			warm:	or	r24, r3, r3	/* startType to r24 */start:	/* Zero-out registers: r0 & SPRGs */	xor     r0,r0,r0	mtspr   272,r0	mtspr   273,r0	mtspr   274,r0	mtspr   275,r0        /* if processor 1, branch to processor 1 code */        lis	r3, HIADJ(RAVEN_BASE_ADRS)        ori	r3, r3, LO(RAVEN_BASE_ADRS)        lwz	r4, RAVEN_MPC_GCSR(r3)	/* read GCSR */        andis.	r4, r4,0x0003		/* Extract the MIDx bits from GCSR */        bc	12, 2, clear_proc_0	/* If processor 0, skip this */	stw	r4, RAVEN_MPC_GPREG1_L(r3) /* clear processor 1 position */        b       start_rom_processing clear_proc_0: 	stw	r4, RAVEN_MPC_GPREG0_L(r3)	/* clear processor 0 position */start_rom_processing:        /* initialize the stack pointer */        lis     sp, HI(STACK_ADRS)        ori     sp, sp, LO(STACK_ADRS)	/*	 *	Set MPU/MSR to a known state	 *	Turn on FP	 */	andi.	r3, r3, 0	ori	r3, r3, 0x2000	sync	mtmsr 	r3	isync	/* Init the floating point control/status register */	mtfsfi  7,0x0	mtfsfi  6,0x0	mtfsfi  5,0x0	mtfsfi  4,0x0	mtfsfi  3,0x0	mtfsfi  2,0x0	mtfsfi  1,0x0	mtfsfi  0,0x0	isync	/* Initialize the floating point data regsiters to a known state */	bl	ifpdr_value	.long	0x3f800000	/* 1.0 */ifpdr_value:	mfspr	r3,8	lfs	f0,0(r3)	lfs	f1,0(r3)	lfs	f2,0(r3)	lfs	f3,0(r3)	lfs	f4,0(r3)	lfs	f5,0(r3)	lfs	f6,0(r3)	lfs	f7,0(r3)	lfs	f8,0(r3)	lfs	f9,0(r3)	lfs	f10,0(r3)	lfs	f11,0(r3)	lfs	f12,0(r3)	lfs	f13,0(r3)	lfs	f14,0(r3)	lfs	f15,0(r3)	lfs	f16,0(r3)	lfs	f17,0(r3)	lfs	f18,0(r3)	lfs	f19,0(r3)	lfs	f20,0(r3)	lfs	f21,0(r3)	lfs	f22,0(r3)	lfs	f23,0(r3)	lfs	f24,0(r3)	lfs	f25,0(r3)	lfs	f26,0(r3)	lfs	f27,0(r3)	lfs	f28,0(r3)	lfs	f29,0(r3)	lfs	f30,0(r3)	lfs	f31,0(r3)	sync	/*	 *	Set MPU/MSR to a known state	 *	Turn off FP	 */	andi.	r3, r3, 0	sync	mtmsr 	r3	isync	/* Init the Segment registers */	andi.	r3, r3, 0	isync	mtsr    0,r3	isync	mtsr    1,r3	isync	mtsr    2,r3	isync	mtsr    3,r3	isync	mtsr    4,r3	isync	mtsr    5,r3	isync	mtsr    6,r3	isync	mtsr    7,r3	isync	mtsr    8,r3	isync	mtsr    9,r3	isync	mtsr    10,r3	isync	mtsr    11,r3	isync	mtsr    12,r3	isync	mtsr    13,r3	isync	mtsr    14,r3	isync	mtsr    15,r3	isync	/* Turn off the GLANCE - L2 Cache */	lis	r3, HI(SYS_REG_SXCCR_A)	ori	r3, r3, 0x8000	addis	r4, r0, 0x0	ori	r4, r4, 0x0070	stb	r4, 0x0(r3)	/* Turn off data and instruction cache control bits */		mfspr   r3, HID0	isync	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */	sync	isync	mtspr	HID0, r4		/* HID0 = r4 */	isync	/* Get cpu type */	mfspr   r28, PVR	rlwinm  r28, r28, 16, 16, 31	/* invalidate the MPU's data/instruction caches */	lis	r3, 0x0	cmpli   0, 0, r28, CPU_TYPE_750	beq     CPU_IS_750	cmpli	0, 0, r28, CPU_TYPE_603	beq	CPU_IS_603	cmpli	0, 0, r28, CPU_TYPE_603E	beq	CPU_IS_603        cmpli   0, 0, r28, CPU_TYPE_603P        beq     CPU_IS_603        cmpli   0, 0, r28, CPU_TYPE_604R        bne     CPU_NOT_604RCPU_IS_604R:        lis     r3, 0x0        mtspr   HID0, r3        /* disable the caches */        isync        ori     r4, r4, 0x0002  /* disable BTAC by setting bit 30 */CPU_NOT_604R:	ori	r3, r3, 0x0C00		/* r3 has invalidate bits set */CPU_IS_603:	ori	r3, r3, 0xC000		/* r3 has enable and bits set */	or	r4, r4, r3		/* set bits */	sync	isync	mtspr   HID0, r4		/* HID0 = r4 */	andc	r4, r4, r3		/* clear bits */	isync	cmpli   0, 0, r28, CPU_TYPE_604	beq	CPU_IS_604	cmpli   0, 0, r28, CPU_TYPE_604E	beq	CPU_IS_604        cmpli   0, 0, r28, CPU_TYPE_604R        beq     CPU_IS_604        cmpli   0, 0, r28, CPU_TYPE_750        beq     CPU_IS_604	mtspr	HID0, r4	isync#ifdef USER_I_CACHE_ENABLE 	b	I_CACHE_ON_603#else	b	CACHE_ENABLE_DONE#endifCPU_IS_750:#ifdef USER_I_CACHE_ENABLE        mfspr   r3,HID0        sync        addi    r4,r0,0x0800        or      r3,r4,r3        mtspr   HID0,r3         /* set ICFI (bit 16) */        sync        andc    r3,r3,r4        mtspr   HID0,r3         /* clear ICFI (bit 16) */        sync	addi    r3,r0,0xFFFFDFFF /* Clear ILOCK (bit 18) */        and     r3,r3,r4         mtspr   HID0,r3        sync        ori     r3,r3,0x8000    /* Set ICE (bit 16) */	mtspr   HID0,r3        sync#endif        b       CACHE_ENABLE_DONECPU_IS_604:	lis	r5, 0x0	ori	r5, r5, 0x1000	mtspr	CTR, r5LOOP_DELAY:	nop	bdnz	LOOP_DELAY	isync	mtspr 	HID0, r4	isync	/* turn the Instruction cache ON for faster FLASH ROM boots */#ifdef USER_I_CACHE_ENABLE         ori     r4, r4, 0x8800		/* set ICE & ICFI bit */        isync                           /* Synchronize for ICE enable */	b	WRITE_R4I_CACHE_ON_603:	ori	r4, r4, 0x8800		/* set ICE & ICFI bit */        rlwinm  r3, r4, 0, 21, 19	/* clear the ICFI bit */        /*         * The setting of the instruction cache enable (ICE) bit must be         * preceded by an isync instruction to prevent the cache from being         * enabled or disabled while an instruction access is in progress.         */	isyncWRITE_R4:        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */	cmpli   0, 0, r28, CPU_TYPE_604	beq    	CACHE_ENABLE_DONE 	cmpli   0, 0, r28, CPU_TYPE_604E	beq    	CACHE_ENABLE_DONE 	cmpli   0, 0, r28, CPU_TYPE_604R	beq    	CACHE_ENABLE_DONE 	cmpli   0, 0, r28, CPU_TYPE_750	beq    	CACHE_ENABLE_DONE         mtspr   HID0, r3                /* using 2 consec instructions */                                        /* PPC603 recommendation */#endifCACHE_ENABLE_DONE:        /*         * Muliple Processor System Setup         *         * Since the CPUs share all of the hardware on the board,         * only one processor needs to initialize it.  Therefore, CPU_0 will be         * responsible for initializing the common hardware on the board.         *         */	/* 	 * Must test for which processor this is. 	 * If processor 0, then let it continue. 	 * If processor 1, then park it here. 	 */  	lis	r3, HIADJ(RAVEN_BASE_ADRS) 	ori	r3, r3, LO(RAVEN_BASE_ADRS) 	lwz	r4,RAVEN_MPC_GCSR(r3)	/* read GCSR */ 	andis.	r4,r4,0x0003		/* Extract the MIDx bits from GCSR */ 	bc	4,2,parkcpu1		/* If not processor 0, park */ 	b	finish_romInit		/* branch to finish romInit: CPU_0. */ parkcpu1: 	b	parkcpu1 finish_romInit:        /* Enhance execution based on cpu type */        cmpli   0, 0, r28, CPU_TYPE_603        beq     raven3        cmpli   0, 0, r28, CPU_TYPE_603E        beq     raven3        cmpli   0, 0, r28, CPU_TYPE_603P        beq     raven3        /* enable branch history table for the 604 and 750 */        mfspr   r3, HID0        ori     r3, r3, _PPC_HID0_BHTE        cmpli   0, 0, r28, CPU_TYPE_750        beq     enhanceAll        /*         * CPU is not 750 or 603x so it must be a 604x.         * Disable sequential instruction execution (go superscalar) and         * enable branch history table for the 604.         */        ori     r3, r3, _PPC_HID0_SIED