/* ravenPci.c - Raven PCI bus bridge chip initialization *//* Copyright 1984-2000 Wind River Systems, Inc. *//* Copyright 1996,1997,1998 Motorola, Inc., All Rights Reserved *//*modification history--------------------01b,20jan00,dat  merged with latest mcg drop01a,12dec97,rhk  created by Motorola.*//*DESCRIPTIONThe following contains the initialization routinesfor the Raven, a Host PCI Bridge/Memory Controller used inMotorola's PowerPC based boards..CS   Initialize the RAVEN MPC registers.   notes:   1. For the standard vxWorks configuration the  MPC to      PCI mapping registers are initialized to the PReP      model with some additions:   MPC Address Range   PCI Address Range      Definition   -----------------   -----------------   -----------------   80000000 BF7FFFFF   00000000 3F7FFFFF   ISA/PCI I/O space   C0000000 FCFFFFFF   00000000 3CFFFFFF   ISA/PCI Mem space w/MPIC   FD000000 FDFFFFFF   00000000 00FFFFFF   ISA/PCI Mem space   FE000000 FE7FFFFF   00000000 007FFFFF   ISA/PCI I/O space   2. This assignments do not include the entire PReP PCI      address space, this is due to the conflicting local      resources of the H/W.   3. When EXTENDED_VME is defined the mapping is as follows:   MPC Address Range   PCI Address Range      Definition   -----------------   ------------------  -----------------   10000000 FBFFFFFF   10000000 FBFFFFFF   VME address space (1)   FC000000 FCFFFFFF   FC000000 FCFFFFFF   MPIC/Reg space   FD000000 FDFFFFFF   FD000000 FDFFFFFF   ISA/PCI Memory space   FE000000 FE7FFFFF   00000000 007FFFFF   ISA/PCI I/O space   Note 1, the starting address is controlled by the macro   VME_A32_MSTR_LOCAL.CE*//* includes *//* defines */#define RAVEN_ADDR( reg )        ( RAVEN_BASE_ADRS + reg )#define RAVEN_WRITE8( writeAddr, data )  ( *(UINT8 *)(writeAddr) = data )#define RAVEN_WRITE16( writeAddr, data )  ( *(UINT16 *)(writeAddr) = data )#define RAVEN_WRITE32( writeAddr, data )  ( *(UINT32 *)(writeAddr) = data )/* typedefs *//* globals *//* forward declarations *//********************************************************************************* sysRavenInit - initialize the Raven registers** This function performs the first portion of the required initialization * of the Raven registers, and sets up the CPU->PCI windows.** RETURNS: N/A*/void sysRavenInit (void)    {    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_GCSR), 0 );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MARB), 0x0703 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_PADJ), 0xBE );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MEREN), 0 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MERST), 0xFF );    EIEIO_SYNC;    /* initially set the CPU->PCI attribute registers to disabled */    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT0), 0 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT1), 0 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT2), 0 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT3), 0 );    EIEIO_SYNC;    /* Do all of the CPU to PCI window registers */    /* MSADD0, MSOFF0, MSATT0 registers */    RAVEN_WRITE32( RAVEN_ADDR(RAVEN_MPC_MSADD0), 		   ((CPU2PCI_ADDR0_START<<16) | CPU2PCI_ADDR0_END) );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MSOFF0), CPU2PCI_OFFSET0 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT0), CPU2PCI_MSATT0 );    EIEIO_SYNC;    /* MSADD1, MSOFF1, MSATT1 registers */    RAVEN_WRITE32( RAVEN_ADDR(RAVEN_MPC_MSADD1),		   ((CPU2PCI_ADDR1_START<<16) | CPU2PCI_ADDR1_END) );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MSOFF1), CPU2PCI_OFFSET1 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT1), CPU2PCI_MSATT1 );    EIEIO_SYNC;    /* MSADD2, MSOFF2, MSATT2 registers */        RAVEN_WRITE32( RAVEN_ADDR(RAVEN_MPC_MSADD2),                   ((CPU2PCI_ADDR2_START<<16) | CPU2PCI_ADDR2_END) );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MSOFF2), CPU2PCI_OFFSET2 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT2), CPU2PCI_MSATT2 );    EIEIO_SYNC;    /*     * PCI address space 3 registers supports config. space access and     * special cycle generation.  It should be configured for I/O space.     */    RAVEN_WRITE32( RAVEN_ADDR(RAVEN_MPC_MSADD3),                   ((CPU2PCI_ADDR3_START<<16) | CPU2PCI_ADDR3_END) );    EIEIO_SYNC;    RAVEN_WRITE16( RAVEN_ADDR(RAVEN_MPC_MSOFF3), CPU2PCI_OFFSET3 );    EIEIO_SYNC;    RAVEN_WRITE8( RAVEN_ADDR(RAVEN_MPC_MSATT3), CPU2PCI_MSATT3 );    EIEIO_SYNC;    }/******************************************************************************** sysRavenInitPciExt - initialize the extended portion of the Raven PCI header** This routine initializes the extended portion of the PCI header for the* Motorola Raven ISA Bridge Controller (IBC).** RETURNS: OK, or ERROR if...**/STATUS sysRavenInitPciExt    (    int busNo,          /* bus number */    int deviceNo,       /* device number */    int funcNo          /* function number */    )    {    /*     * Init Raven's MPIC control register access addresses in I/O and     * memory spaces:     *     * IOSPACE  - 0x00000000  [no access]     * MEMSPACE - 0x3C000000  [MPIC_PCI_BASE_ADRS]     */    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_0,                      0x00000000);    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_1,                      MPIC_PCI_BASE_ADRS);    /*     *  Init Raven's Slave decoders (range/offset/attributes)     *     *  These decoders map addresses on the PCI bus to the CPU for     *  access to local DRAM.     *     *  Because hardware can read past real memory, it is necessary to disable     *  Read Ahead for the last 64k of physical memory (DRAM).     */    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD0,                      PCI2CPU_ADDR0_RANGE);    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF0,                      PCI2CPU_OFFSET0);    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT0,                      PCI2CPU_ATT0);    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD1,                      PCI2CPU_ADDR1_RANGE);    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF1,                      PCI2CPU_OFFSET1);    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT1,                      PCI2CPU_ATT1);    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD2,                      PCI2CPU_ADDR2_RANGE);    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF2,                      PCI2CPU_OFFSET2);    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT2,                      PCI2CPU_ATT2);    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD3,                      PCI2CPU_ADDR3_RANGE);    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF3,                      PCI2CPU_OFFSET3);    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT3,                      PCI2CPU_ATT3);    /*     *  Enable Raven's PCI master capability and MEM space     *  (i.e., enable PCI space decoders).     */    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_COMMAND, 0x0006);    return(OK);    }/******************************************************************************** sysRavenErrClr - Clear error conditions in Raven** This routine clears any existing errors in the Motorola Raven PCI Host Bridge* Controller.** RETURNS: N/A*/void sysRavenErrClr (void)    {    /* Clear MPC Error Status register */    sysOutByte ((RAVEN_BASE_ADRS + RAVEN_MPC_MERST), RAVEN_MPC_MERST_CLR);    /* get and clear Raven PCI status reg */    pciConfigOutWord (sysRavPciBusNo, sysRavPciDevNo, sysRavPciFuncNo,                       PCI_CFG_STATUS,                      RAVEN_PCI_CFG_STATUS_DPAR | RAVEN_PCI_CFG_STATUS_SIGTA |                      RAVEN_PCI_CFG_STATUS_RCVTA | RAVEN_PCI_CFG_STATUS_RCVMA |                      RAVEN_PCI_CFG_STATUS_SIGSE | RAVEN_PCI_CFG_STATUS_RCVPE);    }