?? fpga313czkz.tan.qmsg
字號:
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk_in register lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\] register lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] 9.0 ns " "Info: Slack time is 9.0 ns for clock \"clk_in\" between source register \"lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]\" and destination register \"lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "62.5 MHz 16.0 ns " "Info: Fmax is 62.5 MHz (period= 16.0 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "21.400 ns + Largest register register " "Info: + Largest register to register requirement is 21.400 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 25.000 ns " "Info: + Latch edge is 25.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk_in 25.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk_in\" is 25.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk_in 25.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk_in\" is 25.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_in 1 CLK PIN_125 19 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_125; Fanout = 19; CLK Node = 'clk_in'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { clk_in } "NODE_NAME" } "" } } { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 59 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] 2 REG LC3_E16 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_E16; Fanout = 4; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "2.500 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_in 1 CLK PIN_125 19 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_125; Fanout = 19; CLK Node = 'clk_in'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { clk_in } "NODE_NAME" } "" } } { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 59 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\] 2 REG LC5_E16 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_E16; Fanout = 3; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "2.500 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns - " "Info: - Micro setup delay of destination is 2.500 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.400 ns - Longest register register " "Info: - Longest register to register delay is 12.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\] 1 REG LC5_E16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_E16; Fanout = 3; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns LessThan~172 2 COMB LC2_E13 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC2_E13; Fanout = 1; COMB Node = 'LessThan~172'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "3.900 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] LessThan~172 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns LessThan~167 3 COMB LC3_E13 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC3_E13; Fanout = 1; COMB Node = 'LessThan~167'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "1.500 ns" { LessThan~172 LessThan~167 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 8.300 ns LessThan~161 4 COMB LC6_E13 19 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 8.300 ns; Loc. = LC6_E13; Fanout = 19; COMB Node = 'LessThan~161'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "2.900 ns" { LessThan~167 LessThan~161 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.700 ns) 12.400 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] 5 REG LC3_E16 4 " "Info: 5: + IC(2.400 ns) + CELL(1.700 ns) = 12.400 ns; Loc. = LC3_E16; Fanout = 4; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "4.100 ns" { LessThan~161 lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 58.06 % " "Info: Total cell delay = 7.200 ns ( 58.06 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns 41.94 % " "Info: Total interconnect delay = 5.200 ns ( 41.94 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "12.400 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] LessThan~172 LessThan~167 LessThan~161 lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "12.400 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] LessThan~172 LessThan~167 LessThan~161 lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 2.200ns 0.000ns 0.600ns 2.400ns } { 0.000ns 1.700ns 1.500ns 2.300ns 1.700ns } } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "5.300 ns" { clk_in lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "5.300 ns" { clk_in clk_in~out lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "12.400 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] LessThan~172 LessThan~167 LessThan~161 lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "12.400 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[12] LessThan~172 LessThan~167 LessThan~161 lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } { 0.000ns 2.200ns 0.000ns 0.600ns 2.400ns } { 0.000ns 1.700ns 1.500ns 2.300ns 1.700ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk_1us register main:m2\|mach_next.JudgeParallelFull register main:m2\|mach_next.AckParallel 1.3 ns " "Info: Minimum slack time is 1.3 ns for clock \"clk_1us\" between source register \"main:m2\|mach_next.JudgeParallelFull\" and destination register \"main:m2\|mach_next.AckParallel\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Shortest register register " "Info: + Shortest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:m2\|mach_next.JudgeParallelFull 1 REG LC1_E10 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E10; Fanout = 5; REG Node = 'main:m2\|mach_next.JudgeParallelFull'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns main:m2\|mach_next.AckParallel 2 REG LC2_E10 19 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC2_E10; Fanout = 19; REG Node = 'main:m2\|mach_next.AckParallel'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "1.800 ns" { main:m2|mach_next.JudgeParallelFull main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "1.800 ns" { main:m2|mach_next.JudgeParallelFull main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "1.800 ns" { main:m2|mach_next.JudgeParallelFull main:m2|mach_next.AckParallel } { 0.0ns 0.6ns } { 0.0ns 1.2ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.500 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.500 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 6.400 ns " "Info: + Latch edge is 6.400 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk_1us 1000.000 ns 6.400 ns 50 " "Info: Clock period of Destination clock \"clk_1us\" is 1000.000 ns with offset of 6.400 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 6.400 ns " "Info: - Launch edge is 6.400 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk_1us 1000.000 ns 6.400 ns 50 " "Info: Clock period of Source clock \"clk_1us\" is 1000.000 ns with offset of 6.400 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1us destination 6.000 ns + Longest register " "Info: + Longest clock path from clock \"clk_1us\" to destination register is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_1us 1 CLK LC1_E13 370 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E13; Fanout = 370; CLK Node = 'clk_1us'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { clk_1us } "NODE_NAME" } "" } } { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.000 ns) + CELL(0.000 ns) 6.000 ns main:m2\|mach_next.AckParallel 2 REG LC2_E10 19 " "Info: 2: + IC(6.000 ns) + CELL(0.000 ns) = 6.000 ns; Loc. = LC2_E10; Fanout = 19; REG Node = 'main:m2\|mach_next.AckParallel'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 100.00 % " "Info: Total interconnect delay = 6.000 ns ( 100.00 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1us source 6.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_1us\" to source register is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_1us 1 CLK LC1_E13 370 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E13; Fanout = 370; CLK Node = 'clk_1us'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { clk_1us } "NODE_NAME" } "" } } { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.000 ns) + CELL(0.000 ns) 6.000 ns main:m2\|mach_next.JudgeParallelFull 2 REG LC1_E10 5 " "Info: 2: + IC(6.000 ns) + CELL(0.000 ns) = 6.000 ns; Loc. = LC1_E10; Fanout = 5; REG Node = 'main:m2\|mach_next.JudgeParallelFull'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 100.00 % " "Info: Total interconnect delay = 6.000 ns ( 100.00 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" { } { { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" { } { { "main.v" "" { Text "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 113 -1 0 } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } } 0} } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "1.800 ns" { main:m2|mach_next.JudgeParallelFull main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "1.800 ns" { main:m2|mach_next.JudgeParallelFull main:m2|mach_next.AckParallel } { 0.0ns 0.6ns } { 0.0ns 1.2ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.AckParallel } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } "NODE_NAME" } "" } } { "d:/quartus5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5.0/bin/Technology_Viewer.qrui" "6.000 ns" { clk_1us main:m2|mach_next.JudgeParallelFull } { 0.0ns 6.0ns } { 0.0ns 0.0ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk_in register lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\] register lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] 1.4 ns " "Info: Minimum slack time is 1.4 ns for clock \"clk_in\" between source register \"lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]\" and destination register \"lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.900 ns + Shortest register register " "Info: + Shortest register to register delay is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\] 1 REG LC2_E16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E16; Fanout = 3; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|counter_cell\[9\]~COUT 2 COMB LC2_E16 3 " "Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = LC2_E16; Fanout = 3; COMB Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|counter_cell\[9\]~COUT'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "1.200 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[9] lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 1.900 ns lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] 3 REG LC3_E16 4 " "Info: 3: + IC(0.000 ns) + CELL(0.700 ns) = 1.900 ns; Loc. = LC3_E16; Fanout = 4; REG Node = 'lpm_counter:cnt1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]'" { } { { "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" "" { Report "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz_cmp.qrpt" Compiler "fpga313czkz" "UNKNOWN" "V1" "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/db/fpga313czkz.quartus_db" { Floorplan "E:/my_work/313/操作控制板_歸檔/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/" "" "0.700 ns" { lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 100.00 % " "Info: Total cell delay = 1.900 ns ( 100.00 % )" { } { } 0} } { { "E:/my_work/313/操作控制板_歸檔/H?? 快捷鍵說明
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