?? usb20c_sim.rpt
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Project Information e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/15/2004 17:33:32
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
usb20c_sim
EPM7128SLC84-15 8 5 8 28 18 21 %
User Pins: 8 5 8
Project Information e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'nPKTEND' is stuck at VCC
Project Information e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
usb20c_sim@36 Addr0
usb20c_sim@37 Addr1
usb20c_sim@1 Clock
usb20c_sim@17 DataBus0
usb20c_sim@22 DataBus1
usb20c_sim@24 DataBus2
usb20c_sim@25 DataBus3
usb20c_sim@27 DataBus4
usb20c_sim@28 DataBus5
usb20c_sim@29 DataBus6
usb20c_sim@30 DataBus7
usb20c_sim@34 DMADir
usb20c_sim@21 DMAing
usb20c_sim@35 nDMACS
usb20c_sim@31 nDMAOE
usb20c_sim@11 nDMARD
usb20c_sim@16 nDMAWR
usb20c_sim@20 nFEmpty
usb20c_sim@18 nFFull
usb20c_sim@33 nPKTEND
usb20c_sim@9 nPWR
Project Information e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
** FILE HIERARCHY **
|addrdecode:1|
|datagenerate:2|
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
***** Logic for device 'usb20c_sim' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R
E E E E E E E E E E E
n S S S S S V S S S S S S
D E E E E E C C E E E V E E E
M R n R R R R C l R R R C R R R
A V P V G V V V I G o G G G V V V C V V V
R E W E N E E E N N c N N N E E E I E E E
D D R D D D D D T D k D D D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
nDMAWR | 16 70 | RESERVED
DataBus0 | 17 69 | RESERVED
nFFull | 18 68 | RESERVED
GND | 19 67 | RESERVED
nFEmpty | 20 66 | VCCIO
DMAing | 21 65 | RESERVED
DataBus1 | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
DataBus2 | 24 62 | #TCK
DataBus3 | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
DataBus4 | 27 59 | GND
DataBus5 | 28 58 | RESERVED
DataBus6 | 29 57 | RESERVED
DataBus7 | 30 56 | RESERVED
nDMAOE | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
n D n A A V R R R G V R R R G R R R R R V
P M D d d C E E E N C E E E N E E E E E C
K A M d d C S S S D C S S S D S S S S S C
T D A r r I E E E I E E E E E E E E I
E i C 0 1 O R R R N R R R R R R R R O
N r S V V V T V V V V V V V V
D E E E E E E E E E E E
D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 6/16( 37%) 2/ 8( 25%) 1/16( 6%) 13/36( 36%)
B: LC17 - LC32 3/16( 18%) 7/ 8( 87%) 2/16( 12%) 12/36( 33%)
C: LC33 - LC48 15/16( 93%) 8/ 8(100%) 16/16(100%) 31/36( 86%)
D: LC49 - LC64 3/16( 18%) 5/ 8( 62%) 0/16( 0%) 4/36( 11%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 1/16( 6%) 0/ 8( 0%) 1/16( 6%) 5/36( 13%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 24/64 ( 37%)
Total logic cells used: 28/128 ( 21%)
Total shareable expanders used: 18/128 ( 14%)
Total Turbo logic cells used: 28/128 ( 21%)
Total shareable expanders not available (n/a): 2/128 ( 1%)
Average fan-in: 6.25
Total fan-in: 175
Total input pins required: 8
Total fast input logic cells required: 0
Total output pins required: 5
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 28
Total flipflops required: 20
Total product terms required: 95
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 15
Synthesized logic cells: 1/ 128 ( 0%)
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 (57) (D) INPUT 0 0 0 0 0 10 8 Addr0
37 (56) (D) INPUT 0 0 0 0 0 10 8 Addr1
1 - - INPUT 0 0 0 0 0 2 2 Clock
17 25 B BIDIR 0 0 0 4 2 2 2 DataBus0
22 17 B BIDIR 2 1 0 4 5 2 2 DataBus1
24 46 C BIDIR 4 2 1 4 7 1 2 DataBus2
25 45 C BIDIR 0 0 0 4 2 0 2 DataBus3
27 43 C BIDIR 2 1 0 4 4 2 2 DataBus4
28 40 C BIDIR 4 2 1 4 6 1 2 DataBus5
29 38 C BIDIR 0 0 0 4 2 0 2 DataBus6
30 37 C BIDIR 2 0 0 4 4 1 0 DataBus7
34 (61) (D) INPUT 0 0 0 0 0 0 2 DMADir
21 (19) (B) INPUT 0 0 0 0 0 10 10 DMAing
20 (21) (B) INPUT 0 0 0 0 0 1 1 nFEmpty
18 (24) (B) INPUT 0 0 0 0 0 1 1 nFFull
9 (8) (A) INPUT 0 0 0 0 0 10 8 nPWR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 25 B TRI/FF t 0 0 0 4 2 2 2 DataBus0
22 17 B TRI/FF t 2 1 0 4 5 2 2 DataBus1
24 46 C TRI/FF t 4 2 1 4 7 1 2 DataBus2
25 45 C TRI/FF t 0 0 0 4 2 0 2 DataBus3
27 43 C TRI/FF t 2 1 0 4 4 2 2 DataBus4
28 40 C TRI/FF t 4 2 1 4 6 1 2 DataBus5
29 38 C TRI/FF t 0 0 0 4 2 0 2 DataBus6
30 37 C TRI/FF t 2 0 0 4 4 1 0 DataBus7
35 59 D OUTPUT t 0 0 0 0 4 0 0 nDMACS
31 35 C OUTPUT t 0 0 0 0 2 0 0 nDMAOE
11 5 A FF t ! 0 0 0 6 2 3 0 nDMARD
16 27 B FF t ! 0 0 0 6 2 10 1 nDMAWR
33 64 D OUTPUT t 0 0 0 0 0 0 0 nPKTEND
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
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