?? test.v
字號:
`timescale 10ns/100ps
module testBench;
reg clock,d,reset;
dff d1(q,clock,d,reset); // module substantiation
always // clock
#10 clock=~clock;
initial begin // test procedure
$monitor($time," clock= %b d= %b reset= %b q= %b",clock,d,reset,q);
#1 clock=0;reset=0;
#1 d=1;
#1 reset=1;
#2 reset=0;
#7 d=0;
#25 d=1;
#20 reset=1;
#2 reset=0;
#10 $finish;
end
endmodule
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