library ieee;
use ieee.std_logic_1164.all;

entity pn_correlator is
    generic (
        K : std_logic_vector (7 downto 0) := "10001101");
    port (
        clk, reset, data_ch       : in  std_logic;
        wr, pn_lock, wr_addr_srst : out std_logic;
        wr_data                   : out std_logic_vector(7 downto 0));

end pn_correlator;

architecture structure of pn_correlator is
    component pn_correlation is
        generic (
            K : std_logic_vector (7 downto 0) := "10001101");
        port (
            clk, reset, pn_acq, data_ch : in  std_logic;
            pn_fnd                      : out std_logic;
            wr_data                     : out std_logic_vector (7 downto 0));
    end component pn_correlation;

    component pn_correlation_fsm is
        port (
            clk, reset, pn_fnd  : in  std_logic;
            wr_addr_srst        : out std_logic;
            pn_lock, pn_acq, wr : out std_logic);
    end component pn_correlation_fsm;
    
    signal pn_fnd, pn_acq : std_logic;
    
begin  -- structure
    
    pn_correlation_inst: pn_correlation
        generic map (
            K => K)
        port map(
            clk => clk,
            reset => reset,
            pn_acq => pn_acq,
            data_ch => data_ch,
            pn_fnd => pn_fnd,
            wr_data => wr_data);
    

    pn_correlation_fsm_inst: pn_correlation_fsm
        port map(
            clk => clk,
            reset => reset,
            pn_fnd => pn_fnd,
            wr_addr_srst => wr_addr_srst,
            pn_lock => pn_lock,
            pn_acq => pn_acq,
            wr => wr);

end structure;