?? pn_correlation.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ch_fifo_pack.all;
entity pn_correlation is
generic (
K : std_logic_vector (7 downto 0) := "10001101");
port (
clk, reset, pn_acq, data_ch : in std_logic;
pn_fnd : out std_logic;
wr_data : out std_logic_vector (7 downto 0));
end pn_correlation;
architecture rtl of pn_correlation is
signal sr_data : std_logic_vector(7 downto 0);
begin -- rtl
wr_data <= sr_data;
-- Serial to parrallel converter
process (clk, reset)
begin -- process
if reset = '1' then -- asynchronous reset (active high)
sr_data <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
sr_data <= data_ch & sr_data(7 downto 1);
end if;
end process;
-- pn_rake
pn_rake: process (clk, reset)
variable result : std_logic_vector (7 downto 0);
variable agree, disagree, correlation : integer;
begin -- process pn_rake
if reset = '1' then -- asynchronous reset (active high)
pn_fnd <= '0';
elsif rising_edge(clk) then -- rising clock edge
-- default
pn_fnd <= '0';
if pn_acq = '1' then
for j in 0 to 7 loop
if K(j) = '1' then
result(j) := K(j) and sr_data(j);
else
result(j) := not K(j) and not sr_data(j);
end if;
end loop; -- j
--
agree := 0;
disagree := 0;
for i in 0 to 7 loop
case result(i) is
when '0' =>
disagree := disagree + 1;
when '1' =>
agree := agree + 1;
when others => null;
end case;
end loop; -- i
correlation := agree - disagree;
if correlation = 8 then
pn_fnd <= '1';
else
pn_fnd <= '0';
end if;
end if;
end if;
end process pn_rake;
end rtl;
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