library ieee;
use ieee.std_logic_1164.all;

entity ch_fifo is
    generic (
        K : std_logic_vector (7 downto 0) := "10001101");
    port (
        rd_clk, wr_clk, reset, data_ch, rd                     : in  std_logic;
        pn_lock_rd_clk, almost_full, almost_empty, full, empty : out std_logic;
        rd_data                                                : out std_logic_vector (7 downto 0));
end ch_fifo;

architecture structure of ch_fifo is

    component pn_correlator is
                                generic (
                                    K : std_logic_vector (7 downto 0) := "10001101");
                            port (
                                clk, reset, data_ch       : in  std_logic;
                                wr, pn_lock, wr_addr_srst : out std_logic;
                                wr_data                   : out std_logic_vector(7 downto 0));
    end component pn_correlator;

    component fifo_status is
                              port (
                                  rd_clk, wr_clk, reset, rd, wr, pn_lock, wr_addr_srst : in  std_logic;
                                  rd_addr, wr_addr                                     : out std_logic_vector (10 downto 0);
                                  full, empty, almost_full, half_full, almost_empty    : out std_logic;
                                  pn_lock_rd_clk                                       : out std_logic);
    end component fifo_status;

    component fifo_2048x8 is
                              port (
                                  rd_clk, wr_clk, wr, rd, reset : in  std_logic;
                                  wr_addr, rd_addr              : in  std_logic_vector(10 downto 0);
                                  wr_data                       : in  std_logic_vector (7 downto 0);
                                  rd_data                       : out std_logic_vector (7 downto 0));
    end component fifo_2048x8;

    signal pn_lock, wr, wr_addr_srst : std_logic;
    signal rd_addr, wr_addr : std_logic_vector (10 downto 0);
    signal wr_data : std_logic_vector (7 downto 0);
begin  -- structure

    pn_correlator_inst: pn_correlator
        generic map (
            K => K)
        port map (
            clk => wr_clk,
            reset => reset,
            data_ch => data_ch,
            wr => wr,
            pn_lock => pn_lock,
            wr_addr_srst => wr_addr_srst,
            wr_data => wr_data);

    fifo_status_inst: fifo_status
        port map(
            rd_clk => rd_clk,
            wr_clk => wr_clk,
            reset => reset,
            rd => rd,
            wr => wr,
            pn_lock => pn_lock,
            wr_addr_srst => wr_addr_srst,
            rd_addr => rd_addr,
            wr_addr => wr_addr,
            full => full,
            empty => empty,
            almost_full => almost_full,
            half_full => open,
            almost_empty => almost_empty,
            pn_lock_rd_clk => pn_lock_rd_clk);

    fifo_2048x8_inst : fifo_2048x8
        port map(
            rd_clk => rd_clk,
            wr_clk => wr_clk,
            wr => wr,
            rd => rd,
            reset => reset,
            wr_addr => wr_addr,
            rd_addr =>  rd_addr,
            wr_data => wr_data,
            rd_data => rd_data);    

end structure;