#Build: Synplify Pro 8.5F, Build 001R, Mar  7 2006
#install: C:\Libero\Synplify\Synplify_85F
#OS: Windows XP 5.1
#Hostname: WXP-HUANGKY

#Mon Sep 18 16:29:48 2006

$ Start of Compile
#Mon Sep 18 16:29:48 2006

Synplicity VHDL Compiler, version 3.4.1, Build 137R, built Apr  7 2006
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@N:"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":10:7:10:9|Top entity is set to TOP.
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":9:7:9:9|Synthesizing work.top.def_arch 
@W: CD434 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":106:24:106:26|Signal sw2 in the sensitivity list is not used in the process
@W: CG296 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":106:16:106:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":109:3:109:5|Referenced variable sw1 is not in sensitivity list
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":128:14:128:19|Referenced variable lcd_en is not in sensitivity list
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":9:7:9:9|Synthesizing work.lcd.behavioural 
@N: CD231 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":23:16:23:17|Using onehot encoding for type state_type (warmup="100000000")
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":101:12:101:26|OTHERS clause is not synthesized 
Post processing for work.lcd.behavioural
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal lcd_data[7:4]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal finished. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal lcd_rs. Did you forget the set/reset assignment for this signal?
@N: CL201 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\my_clk_divider.vhd":6:7:6:17|Synthesizing work.clk_divider.def_arch 
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\clockdiv.vhd":5:7:5:14|Synthesizing work.clockdiv.behavioural 
Post processing for work.clockdiv.behavioural
Post processing for work.clk_divider.def_arch
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_block.vhd":8:7:8:16|Synthesizing work.data_block.def_arch 
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\mux2.vhd":5:7:5:10|Synthesizing work.mux2.behavioral 
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\mux2.vhd":23:6:23:19|OTHERS clause is not synthesized 
Post processing for work.mux2.behavioral
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":6:7:6:12|Synthesizing work.count8.behavioral 
@W: CG296 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":21:2:21:8|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":27:23:27:26|Referenced variable data is not in sensitivity list
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":26:11:26:15|Referenced variable sload is not in sensitivity list
Post processing for work.count8.behavioral
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\LED_Flashing.vhd":7:7:7:18|Synthesizing work.led_flashing.behavioral 
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\LED_Flashing.vhd":39:6:39:19|OTHERS clause is not synthesized 
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\binary_counter.vhd":6:7:6:20|Synthesizing work.binary_counter.behavioral 
Post processing for work.binary_counter.behavioral
Post processing for work.led_flashing.behavioral
Post processing for work.data_block.def_arch
Post processing for work.top.def_arch
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Sep 18 16:29:48 2006

###########################################################[
Synplicity Proasic Technology Mapper, Version 8.6.0, Build 155R, Built Apr 11 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.5F
@N: MF249 |Running in 32-bit mode.
@N|Gated clock conversion disabled 


Automatic dissolve at startup in view:work.Data_Block(def_arch) of SW7_count(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.5.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.12.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.6.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.2.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.1.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.8.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.10.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.4.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.21.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.14.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.23.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.17.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.11.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.18.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.19.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.20.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.13.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.7.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.3.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.9.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.15.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.22.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.16.clk_div(clockdiv)
Automatic dissolve at startup in view:work.TOP(def_arch) of CLK_DIVIDER_intance(CLK_DIVIDER)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 26MB peak: 27MB)
Encoding state machine work.lcd(behavioural)-state[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)
Promoting Net SW1_c on CLKINT  I_10
Buffering SW3_c, fanout 16 segments 2
Buffering SW2_c, fanout 19 segments 2
Replicating lcd_en, fanout 22 segments 2
Buffering clk_internal1, fanout 13 segments 2

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 29MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 29MB)

Added 3 Buffers
Added 1 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 29MB)
@N: BN191 |Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap.
Writing Analyst data base C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.srm
@N: BN225 |Writing default property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.map.
Writing EDIF Netlist and constraint files
Found clock TOP|CLK with period 10.00ns 
Found clock TOP|SW6 with period 10.00ns 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net clk_internal1 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[15] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[21] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[14] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[8] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[2] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[6] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[12] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[19] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[18] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[17] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[10] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[16] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[13] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[20] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[3] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[9] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[7] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[1] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[5] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[11] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|Net net[4] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":122:15:122:25|Net lcd_en appears to be a clock source which was not identified. Assuming default frequency.