JDF G
// Created by Project Navigator ver 1.0
PROJECT vga
DESIGN vga
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE generic_dpram.v
SOURCE generic_spram.v
SOURCE sync_check.v
SOURCE vga_clkgen.v
SOURCE vga_colproc.v
SOURCE vga_csm_pb.v
SOURCE vga_cur_cregs.v
SOURCE vga_curproc.v
SOURCE vga_enh_top.v
SOURCE vga_fifo.v
SOURCE vga_fifo_dc.v
SOURCE vga_pgen.v
SOURCE vga_tgen.v
STIMULUS vga_wb_slave.v
SOURCE wb_mast_model.v
STIMULUS vga_wb_master.v
[STATUS-ALL]
vga_enh_top.stxFile=WARNINGS,1113270087
[STRATEGY-LIST]
Normal=True