Release 6.1i - xst G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.21 s | Elapsed : 0.00 / 0.00 s --> Reading design: i2c_master_byte_ctrl.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : i2c_master_byte_ctrl.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : i2c_master_byte_ctrlOutput Format                      : NGCTarget Device                      : xc2s50e-6-tq144---- Source OptionsTop Module Name                    : i2c_master_byte_ctrlAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : i2c_master_byte_ctrl.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO=========================================================================WARNING:Xst:1885 - LSO file is empty, default list of libraries is used=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "i2c_master_bit_ctrl.v"Compiling include file "i2c_master_defines.v"Module <i2c_master_bit_ctrl> compiledCompiling source file "i2c_master_byte_ctrl.v"Compiling include file "i2c_master_defines.v"WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefinedModule <i2c_master_byte_ctrl> compiledNo errors in compilationAnalysis of file <i2c_master_byte_ctrl.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <i2c_master_byte_ctrl>.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 168: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 170: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 172: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 174: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 179: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <i2c_master_byte_ctrl> is correct for synthesis. Analyzing module <i2c_master_bit_ctrl>.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 180: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 189: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 190: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 194: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 195: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <i2c_master_bit_ctrl> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <i2c_master_bit_ctrl>.    Related source file is i2c_master_bit_ctrl.v.    Found finite state machine <FSM_0> for signal <c_state>.    -----------------------------------------------------------------------    | States             | 18                                             |    | Transitions        | 50                                             |    | Inputs             | 6                                              |    | Outputs            | 19                                             |    | Clock              | clk (rising_edge)                              |    | Clock enable       | $n0001 (positive)                              |    | Reset              | nReset (negative)                              |    | Reset type         | asynchronous                                   |    | Reset State        | 000000000000000001                             |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <sda_oen>.    Found 1-bit register for signal <al>.    Found 1-bit register for signal <cmd_ack>.    Found 1-bit register for signal <busy>.    Found 1-bit register for signal <scl_oen>.    Found 1-bit register for signal <dout>.    Found 16-bit subtractor for signal <$n0049> created at line 210.    Found 1-bit register for signal <clk_en>.    Found 1-bit register for signal <cmd_stop>.    Found 16-bit register for signal <cnt>.    Found 1-bit register for signal <dcmd_stop>.    Found 1-bit register for signal <dSCL>.    Found 1-bit register for signal <dscl_oen>.    Found 1-bit register for signal <dSDA>.    Found 1-bit register for signal <sda_chk>.    Found 1-bit register for signal <sSCL>.    Found 1-bit register for signal <sSDA>.    Found 1-bit register for signal <sta_condition>.    Found 1-bit register for signal <sto_condition>.    Summary:	inferred   1 Finite State Machine(s).	inferred  33 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).Unit <i2c_master_bit_ctrl> synthesized.Synthesizing Unit <i2c_master_byte_ctrl>.    Related source file is i2c_master_byte_ctrl.v.    Found finite state machine <FSM_1> for signal <c_state>.    -----------------------------------------------------------------------    | States             | 6                                              |    | Transitions        | 31                                             |    | Inputs             | 9                                              |    | Outputs            | 6                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | nReset (negative)                              |    | Reset type         | asynchronous                                   |    | Reset State        | 000001                                         |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <cmd_ack>.    Found 1-bit register for signal <ack_out>.    Found 3-bit subtractor for signal <$n0021> created at line 185.    Found 4-bit register for signal <core_cmd>.    Found 1-bit register for signal <core_txd>.    Found 3-bit register for signal <dcnt>.    Found 1-bit register for signal <ld>.    Found 1-bit register for signal <shift>.    Found 8-bit register for signal <sr>.    Summary:	inferred   1 Finite State Machine(s).	inferred  20 D-type flip-flop(s).