Flow report for WorkOneBeta
Tue Aug 21 22:08:49 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Tue Aug 21 22:08:49 2007    ;
; Quartus II Version      ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name           ; WorkOneBeta                              ;
; Top-level Entity Name   ; TopLayer                                 ;
; Family                  ; Cyclone                                  ;
; Device                  ; EP1C3T144C8                              ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; No                                       ;
; Total logic elements    ; 426 / 2,910 ( 15 % )                     ;
; Total pins              ; 50 / 104 ( 48 % )                        ;
; Total virtual pins      ; 0                                        ;
; Total memory bits       ; 51,718 / 59,904 ( 86 % )                 ;
; Total PLLs              ; 0 / 1 ( 0 % )                            ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 08/21/2007 22:08:16 ;
; Main task         ; Compilation         ;
; Revision Name     ; WorkOneBeta         ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                              ;
+-----------------------------------+----------------------+---------------+-------------+----------------------+
; Assignment Name                   ; Value                ; Default Value ; Entity Name ; Section Id           ;
+-----------------------------------+----------------------+---------------+-------------+----------------------+
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL   ; Design Compiler      ; <None>        ; --          ; --                   ;
; EDA_INPUT_DATA_FORMAT             ; Edif                 ; --            ; --          ; eda_design_synthesis ;
; EDA_INPUT_VCC_NAME                ; Vdd                  ; --            ; --          ; eda_design_synthesis ;
; EDA_LMF_FILE                      ; altsyn.lmf           ; --            ; --          ; eda_design_synthesis ;
; EDA_OUTPUT_DATA_FORMAT            ; Verilog              ; --            ; --          ; eda_simulation       ;
; EDA_OUTPUT_DATA_FORMAT            ; Verilog              ; --            ; --          ; eda_timing_analysis  ;
; EDA_SIMULATION_TOOL               ; Active-HDL (Verilog) ; <None>        ; --          ; --                   ;
; EDA_TIME_SCALE                    ; 1 ps                 ; --            ; --          ; eda_simulation       ;
; EDA_TIMING_ANALYSIS_TOOL          ; PrimeTime (Verilog)  ; <None>        ; --          ; --                   ;
; PARTITION_NETLIST_TYPE            ; SOURCE               ; --            ; TopLayer    ; Top                  ;
; TOP_LEVEL_ENTITY                  ; TopLayer             ; WorkOneBeta   ; --          ; --                   ;
; VERILOG_INPUT_VERSION             ; SystemVerilog_2005   ; Verilog_2001  ; --          ; --                   ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off                  ; --            ; --          ; --                   ;
+-----------------------------------+----------------------+---------------+-------------+----------------------+


+----------------------------------------+
; Flow Elapsed Time                      ;
+-------------------------+--------------+
; Module Name             ; Elapsed Time ;
+-------------------------+--------------+
; Analysis & Synthesis    ; 00:00:08     ;
; Fitter                  ; 00:00:08     ;
; Assembler               ; 00:00:07     ;
; Classic Timing Analyzer ; 00:00:02     ;
; EDA Netlist Writer      ; 00:00:02     ;
; Total                   ; 00:00:27     ;
+-------------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off WorkOneBeta -c WorkOneBeta
quartus_fit --read_settings_files=off --write_settings_files=off WorkOneBeta -c WorkOneBeta
quartus_asm --read_settings_files=off --write_settings_files=off WorkOneBeta -c WorkOneBeta
quartus_tan --read_settings_files=off --write_settings_files=off WorkOneBeta -c WorkOneBeta --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off WorkOneBeta -c WorkOneBeta