// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This SDF file should be used for Active-HDL (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "TopLayer")
  (DATE "08/21/2007 22:08:48")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|And.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (1097:1097:1097) (1126:1126:1126))
        (PORT datac (1028:1028:1028) (1069:1069:1069))
        (PORT datad (2989:2989:2989) (3105:3105:3105))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE ReadClock\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE Reset\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (531:531:531) (533:533:533))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1335:1335:1335) (1315:1315:1315))
        (PORT clk (1147:1147:1147) (1127:1127:1127))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1792:1792:1792) (1790:1790:1790))
        (PORT datab (749:749:749) (753:753:753))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1337:1337:1337) (1319:1319:1319))
        (PORT clk (1152:1152:1152) (1134:1134:1134))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[2\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (504:504:504) (522:522:522))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[2\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1337:1337:1337) (1319:1319:1319))
        (PORT clk (1152:1152:1152) (1134:1134:1134))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[3\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (491:491:491) (506:506:506))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[3\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1337:1337:1337) (1319:1319:1319))
        (PORT clk (1152:1152:1152) (1134:1134:1134))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[4\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (534:534:534) (537:537:537))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[4\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1337:1337:1337) (1319:1319:1319))
        (PORT clk (1152:1152:1152) (1134:1134:1134))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE ReadU0\|Counter\[5\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (491:491:491) (505:505:505))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE ReadU0\|Counter\[5\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1337:1337:1337) (1319:1319:1319))
        (PORT clk (1152:1152:1152) (1134:1134:1134))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE MeasureStart\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[31\]\~0.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (6227:6227:6227) (6313:6313:6313))
        (PORT datad (1058:1058:1058) (1068:1068:1068))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rIndicatorLight\~57.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (1596:1596:1596) (1632:1632:1632))
        (PORT datad (439:439:439) (440:440:440))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rStartExsitFlag.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aload (2059:2059:2059) (2118:2118:2118))
        (PORT datac (370:370:370) (370:370:370))
        (PORT aclr (1324:1324:1324) (1304:1304:1304))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (PORT ena (1277:1277:1277) (1335:1335:1335))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge aload) regout (956:956:956) (956:956:956))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (535:535:535) (542:542:542))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (539:539:539) (546:546:546))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )