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?? Verilog實現的DDS正弦信號發生器和測頻測相模塊
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// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "08/21/2007 22:08:48"

// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module TopLayer (
	Reset,
	MeasureStart,
	SysClock,
	WaveInOne,
	WaveInTwo,
	Select,
	Increase,
	Decrease,
	Double,
	Halve,
	ReadClock,
	DataOut,
	ReadyFlag,
	LeadFlag,
	ClockOut,
	WaveOutOne,
	WaveOutTwo,
	U4Dir,
	U5Dir,
	U6Dir,
	U7Dir,
	U9Dir,
	U10Dir,
	U11Dir,
	LED0,
	LED1,
	LED2,
	LED3);
input 	Reset;
input 	MeasureStart;
input 	SysClock;
input 	WaveInOne;
input 	WaveInTwo;
input 	Select;
input 	Increase;
input 	Decrease;
input 	Double;
input 	Halve;
input 	ReadClock;
output 	DataOut;
output 	ReadyFlag;
output 	LeadFlag;
output 	ClockOut;
output 	[11:0] WaveOutOne;
output 	[11:0] WaveOutTwo;
output 	U4Dir;
output 	U5Dir;
output 	U6Dir;
output 	U7Dir;
output 	U9Dir;
output 	U10Dir;
output 	U11Dir;
output 	LED0;
output 	LED1;
output 	LED2;
output 	LED3;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("WorkOneBeta_v.sdo");
// synopsys translate_on

wire \MeasureU0|And~combout ;
wire \ReadClock~combout ;
wire \Reset~combout ;
wire \ReadU0|Counter[1]~28 ;
wire \ReadU0|Counter[1]~28COUT1 ;
wire \ReadU0|Counter[2]~27 ;
wire \ReadU0|Counter[2]~27COUT1 ;
wire \ReadU0|Counter[3]~26 ;
wire \ReadU0|Counter[3]~26COUT1 ;
wire \ReadU0|Counter[4]~29 ;
wire \MeasureStart~combout ;
wire \MeasureU0|rFreClockCounter[31]~0_combout ;
wire \MeasureU0|rIndicatorLight~57_combout ;
wire \MeasureU0|rStartExsitFlag~regout ;
wire \MeasureU0|SystemClockDivider|Count[0]~323 ;
wire \MeasureU0|SystemClockDivider|Count[0]~323COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[1]~324 ;
wire \MeasureU0|SystemClockDivider|Count[1]~324COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[2]~325 ;
wire \MeasureU0|SystemClockDivider|Count[2]~325COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[3]~326 ;
wire \MeasureU0|SystemClockDivider|Count[4]~327 ;
wire \MeasureU0|SystemClockDivider|Count[4]~327COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[5]~328 ;
wire \MeasureU0|SystemClockDivider|Count[5]~328COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[6]~329 ;
wire \MeasureU0|SystemClockDivider|Count[6]~329COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[7]~330 ;
wire \MeasureU0|SystemClockDivider|Count[7]~330COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[8]~331 ;
wire \MeasureU0|SystemClockDivider|Count[9]~332 ;
wire \MeasureU0|SystemClockDivider|Count[9]~332COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[10]~333 ;
wire \MeasureU0|SystemClockDivider|Count[10]~333COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[11]~334 ;
wire \MeasureU0|SystemClockDivider|Count[11]~334COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[12]~335 ;
wire \MeasureU0|SystemClockDivider|Count[12]~335COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[13]~336 ;
wire \MeasureU0|SystemClockDivider|Count[14]~337 ;
wire \MeasureU0|SystemClockDivider|Count[14]~337COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[15]~338 ;
wire \MeasureU0|SystemClockDivider|Count[15]~338COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[16]~321 ;
wire \MeasureU0|SystemClockDivider|Count[16]~321COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[17]~320 ;
wire \MeasureU0|SystemClockDivider|Count[17]~320COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[18]~322 ;
wire \MeasureU0|SystemClockDivider|Count[19]~318 ;
wire \MeasureU0|SystemClockDivider|Count[19]~318COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[20]~319 ;
wire \MeasureU0|SystemClockDivider|Count[20]~319COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[21]~339 ;
wire \MeasureU0|SystemClockDivider|Count[21]~339COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[22]~340 ;
wire \MeasureU0|SystemClockDivider|Count[22]~340COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[23]~341 ;
wire \MeasureU0|SystemClockDivider|Count[24]~314 ;
wire \MeasureU0|SystemClockDivider|Count[24]~314COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[25]~315 ;
wire \MeasureU0|SystemClockDivider|Count[25]~315COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[26]~316 ;
wire \MeasureU0|SystemClockDivider|Count[26]~316COUT1 ;
wire \MeasureU0|SystemClockDivider|LessThan0~444_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~452_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~445_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~446_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~447_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~448_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~449_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~450_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~451_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~453_combout ;
wire \MeasureU0|SystemClockDivider|rVirtualClock~regout ;
wire \MeasureU0|rFreClockCounter[1]~1206 ;
wire \MeasureU0|rFreClockCounter[1]~1206COUT1 ;
wire \MeasureU0|rFreClockCounter[2]~1207 ;
wire \MeasureU0|rFreClockCounter[2]~1207COUT1 ;
wire \MeasureU0|rFreClockCounter[3]~1208 ;
wire \MeasureU0|rFreClockCounter[3]~1208COUT1 ;
wire \MeasureU0|rFreClockCounter[4]~1209 ;
wire \MeasureU0|rFreClockCounter[4]~1209COUT1 ;
wire \MeasureU0|rFreClockCounter[5]~1210 ;
wire \MeasureU0|rFreClockCounter[6]~1211 ;
wire \MeasureU0|rFreClockCounter[6]~1211COUT1 ;
wire \MeasureU0|rFreClockCounter[7]~1212 ;
wire \MeasureU0|rFreClockCounter[7]~1212COUT1 ;
wire \MeasureU0|rFreClockCounter[8]~1213 ;
wire \MeasureU0|rFreClockCounter[8]~1213COUT1 ;
wire \MeasureU0|rFreClockCounter[9]~1214 ;
wire \MeasureU0|rFreClockCounter[9]~1214COUT1 ;
wire \MeasureU0|rFreClockCounter[10]~1215 ;
wire \MeasureU0|rFreClockCounter[11]~1216 ;
wire \MeasureU0|rFreClockCounter[11]~1216COUT1 ;
wire \MeasureU0|rFreClockCounter[12]~1217 ;
wire \MeasureU0|rFreClockCounter[12]~1217COUT1 ;
wire \MeasureU0|rFreClockCounter[13]~1218 ;
wire \MeasureU0|rFreClockCounter[13]~1218COUT1 ;
wire \MeasureU0|rFreClockCounter[14]~1219 ;
wire \MeasureU0|rFreClockCounter[14]~1219COUT1 ;
wire \MeasureU0|rFreClockCounter[15]~1220 ;
wire \MeasureU0|rFreClockCounter[16]~1221 ;
wire \MeasureU0|rFreClockCounter[16]~1221COUT1 ;
wire \MeasureU0|rFreClockCounter[17]~1222 ;
wire \MeasureU0|rFreClockCounter[17]~1222COUT1 ;
wire \MeasureU0|rFreClockCounter[18]~1223 ;
wire \MeasureU0|rFreClockCounter[18]~1223COUT1 ;
wire \MeasureU0|rFreClockCounter[19]~1224 ;
wire \MeasureU0|rFreClockCounter[19]~1224COUT1 ;
wire \MeasureU0|rFreClockCounter[20]~1225 ;
wire \MeasureU0|rFreClockCounter[21]~1226 ;
wire \MeasureU0|rFreClockCounter[21]~1226COUT1 ;
wire \MeasureU0|rFreClockCounter[22]~1227 ;
wire \MeasureU0|rFreClockCounter[22]~1227COUT1 ;
wire \MeasureU0|Equal0~359_combout ;
wire \MeasureU0|rFreClockCounter[23]~1228 ;
wire \MeasureU0|rFreClockCounter[23]~1228COUT1 ;
wire \MeasureU0|rFreClockCounter[24]~1229 ;
wire \MeasureU0|rFreClockCounter[24]~1229COUT1 ;
wire \MeasureU0|rFreClockCounter[25]~1230 ;
wire \MeasureU0|rFreClockCounter[26]~1231 ;
wire \MeasureU0|rFreClockCounter[26]~1231COUT1 ;
wire \MeasureU0|Equal0~360_combout ;
wire \MeasureU0|rFreClockCounter[27]~1232 ;
wire \MeasureU0|rFreClockCounter[27]~1232COUT1 ;
wire \MeasureU0|rFreClockCounter[28]~1233 ;
wire \MeasureU0|rFreClockCounter[28]~1233COUT1 ;
wire \MeasureU0|rFreClockCounter[29]~1234 ;
wire \MeasureU0|rFreClockCounter[29]~1234COUT1 ;
wire \MeasureU0|rFreClockCounter[30]~1235 ;
wire \MeasureU0|Equal0~361_combout ;
wire \MeasureU0|Equal0~358_combout ;
wire \MeasureU0|Equal0~362_combout ;
wire \MeasureU0|Equal0~353_combout ;
wire \MeasureU0|Equal0~354_combout ;
wire \MeasureU0|Equal0~355_combout ;
wire \MeasureU0|Equal0~356_combout ;
wire \MeasureU0|Equal0~357_combout ;
wire \MeasureU0|rIndicatorLight~56_combout ;
wire \ReadU0|rReadyFlag~0_combout ;
wire \MeasureU0|rCountFinishFlag~regout ;
wire \MeasureU0|rFreClockCounter[31]~1237_combout ;
wire \ReadU0|Mux0~521 ;
wire \ReadU0|Mux0~522 ;
wire \ReadU0|Mux0~514 ;
wire \ReadU0|Mux0~515 ;
wire \ReadU0|Mux0~518 ;
wire \ReadU0|Mux0~519 ;
wire \ReadU0|Mux0~516 ;
wire \ReadU0|Mux0~517 ;
wire \ReadU0|Mux0~520_combout ;
wire \ReadU0|Mux0~523_combout ;
wire \ReadU0|Mux0~511 ;
wire \ReadU0|Mux0~512 ;
wire \ReadU0|Mux0~504 ;
wire \ReadU0|Mux0~505 ;
wire \ReadU0|Mux0~508 ;
wire \ReadU0|Mux0~509 ;
wire \ReadU0|Mux0~506 ;
wire \ReadU0|Mux0~507 ;
wire \ReadU0|Mux0~510_combout ;
wire \ReadU0|Mux0~513_combout ;
wire \ReadU0|Mux0~524_combout ;
wire \MeasureU0|rFreClockCounter[31]~1239_combout ;
wire \MeasureU0|rFreWaveCounter[1]~1996 ;
wire \MeasureU0|rFreWaveCounter[1]~1996COUT1 ;
wire \MeasureU0|rFreWaveCounter[2]~2018 ;
wire \MeasureU0|rFreWaveCounter[2]~2018COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[1]~228 ;
wire \MeasureU0|rPhaseWaveCounter[1]~228COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[2]~246 ;
wire \MeasureU0|rPhaseWaveCounter[2]~246COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[3]~222 ;
wire \MeasureU0|rPhaseWaveCounter[3]~222COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[4]~236 ;
wire \MeasureU0|rPhaseWaveCounter[4]~236COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[5]~244 ;
wire \MeasureU0|rPhaseWaveCounter[6]~232 ;
wire \MeasureU0|rPhaseWaveCounter[6]~232COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[7]~240 ;
wire \MeasureU0|rPhaseWaveCounter[7]~240COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[8]~247 ;
wire \MeasureU0|rPhaseWaveCounter[8]~247COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[9]~224 ;
wire \MeasureU0|rPhaseWaveCounter[9]~224COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[10]~248 ;
wire \MeasureU0|rPhaseWaveCounter[11]~226 ;
wire \MeasureU0|rPhaseWaveCounter[11]~226COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[12]~230 ;
wire \MeasureU0|rPhaseWaveCounter[12]~230COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[13]~238 ;
wire \MeasureU0|rPhaseWaveCounter[13]~238COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[14]~234 ;
wire \MeasureU0|rPhaseWaveCounter[14]~234COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[15]~242 ;
wire \MeasureU0|rPhaseWaveCounter[16]~252 ;
wire \MeasureU0|rPhaseWaveCounter[16]~252COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[17]~229 ;
wire \MeasureU0|rPhaseWaveCounter[17]~229COUT1 ;
wire \MeasureU0|rPhaseWaveCounter[18]~249 ;
wire \MeasureU0|rPhaseWaveCounter[18]~249COUT1 ;
wire \ReadU0|Counter[5]~31 ;
wire \ReadU0|Counter[5]~31COUT1 ;
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