## Copyright (C) 1991-2007 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

## DATE "08/21/2007 22:08:49"

## 
## Device: Altera EP1C3T144C8 Package TQFP144
## 

## 
## This Tcl script should be used for PrimeTime (Verilog) only
## 

## This file can be sourced in primetime

set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "e:/program files/quartus ii/quartus/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  cyclone_asynch_io_lib.db cyclone_asynch_lcell_lib.db  cyclone_core_mem_lib.db cyclone_lcell_register_lib.db  cyclone_memory_register_lib.db  cyclone_pll_lib.db  alt_vtl.db]

read_verilog  cyclone_all_pt.v 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_verilog  WorkOneBeta.vo
current_design TopLayer
link
## Set variable timing_propagate_single_condition_min_slew to false only for versions 2004.06 and earlier
regexp {([1-9][0-9][0-9][0-9]\.[0-9][0-9])} $sh_product_version dummy version
if { [string compare "2004.06" $version ] != -1 } {
   set timing_propagate_single_condition_min_slew false
}
set_operating_conditions -analysis_type single
read_sdf WorkOneBeta_v.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { SysClock } ] -name SysClock  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { ReadClock } ] -name ReadClock  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { WaveInTwo } ] -name WaveInTwo  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { WaveInOne } ] -name WaveInOne  

set_propagated_clock [all_clocks]
set_clock_groups -asynchronous \
-group {SysClock} \
-group {ReadClock} \
-group {WaveInTwo} \
-group {WaveInOne}
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
set_load -pin_load 10 [get_ports { ClockOut } ]
set_load -pin_load 10 [get_ports { DataOut } ]
set_load -pin_load 10 [get_ports { LED0 } ]
set_load -pin_load 10 [get_ports { LED1 } ]
set_load -pin_load 10 [get_ports { LED2 } ]
set_load -pin_load 10 [get_ports { LED3 } ]
set_load -pin_load 10 [get_ports { LeadFlag } ]
set_load -pin_load 10 [get_ports { ReadyFlag } ]
set_load -pin_load 10 [get_ports { U10Dir } ]
set_load -pin_load 10 [get_ports { U11Dir } ]
set_load -pin_load 10 [get_ports { U4Dir } ]
set_load -pin_load 10 [get_ports { U5Dir } ]
set_load -pin_load 10 [get_ports { U6Dir } ]
set_load -pin_load 10 [get_ports { U7Dir } ]
set_load -pin_load 10 [get_ports { U9Dir } ]
set_load -pin_load 10 [get_ports { WaveOutOne[0] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[10] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[11] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[1] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[2] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[3] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[4] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[5] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[6] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[7] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[8] } ]
set_load -pin_load 10 [get_ports { WaveOutOne[9] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[0] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[10] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[11] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[1] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[2] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[3] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[4] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[5] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[6] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[7] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[8] } ]
set_load -pin_load 10 [get_ports { WaveOutTwo[9] } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##

update_timing