?? workonebeta.map.rpt
字號:
Analysis & Synthesis report for WorkOneBeta
Tue Aug 21 22:08:24 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. Registers Removed During Synthesis
9. General Register Statistics
10. Inverted Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Source assignments for Top-level Entity: |TopLayer
13. Source assignments for Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated
14. Source assignments for Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated
15. Source assignments for DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
16. Source assignments for DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
17. Parameter Settings for User Entity Instance: Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component
18. Parameter Settings for User Entity Instance: Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component
19. Parameter Settings for User Entity Instance: DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component
20. Parameter Settings for User Entity Instance: DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component
21. Analysis & Synthesis Messages
22. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Aug 21 22:08:24 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; WorkOneBeta ;
; Top-level Entity Name ; TopLayer ;
; Family ; Cyclone ;
; Total logic elements ; 474 ;
; Total pins ; 50 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 51,718 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C3T144C8 ; ;
; Top-level entity name ; TopLayer ; WorkOneBeta ;
; Family name ; Cyclone ; Stratix II ;
; Verilog Show LMF Mapping Messages ; Off ; ;
; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -