library ieee; 
use ieee.std_logic_1164.all;  --引用庫
USE ieee.std_logic_arith.ALL;

entity Driver is
    port(Efficiant: out std_logic;  --輸出相素有效
         Latch:out std_logic;       --輸出Latch
         SH: out std_logic;         --輸出SH
         
         data1:out std_logic;       --當前counterc的value 位：10
         data2:out std_logic;       --當前counterc的value 位：11

         clk:in std_logic;          --clock信號
         reset:in std_logic;        --復位

         ccdin:in std_logic;        --ccdin信號
         askdata:in std_logic;      --數據請求
         dataclk: in std_logic;     --與MCU接口的data clock
         addr0:in std_logic;        --地址0
         addr1:in std_logic;        --地址1
         addr2:in std_logic;        --地址2
         addr3:in std_logic);       --地址3

    signal tempSH:std_logic;        --temp輸出，保存上周期輸出信號 (SH)
    signal tempLatch:std_logic;     --temp輸出，保存上周期RS鎖定信號(Latch)
    signal tempEfficiant:std_logic; --temp輸出，包孫上一周期Efficiant信號
end;

architecture behavioral of Driver is
   signal countc:integer range 0 to 4095:=0;
   signal jumpup:integer range 0 to 4095:=0;
   signal jumpdown:integer range 0 to 4095:=0;
   begin
      
   
   process(clk,reset)
     begin
     
     if reset='1' then          --復位
        countc<=0;
        tempSH<='1';
        tempLatch<='0';        
	tempEfficiant<='0';
     elsif clk'event and clk='0' then   --下降沿觸發

        countc<=countc+1;         --計數
        if countc>=2216 then
            countc<=0;
        end if;
	
	if countc=40 then
	   tempEfficiant<='1';
	elsif countc=2211 then
	   tempLatch<='1';
	elsif countc=2200 then
	   tempEfficiant<='0';
	elsif countc=2212 then      --<<----
	   tempSH<='0';               --SH給出高電平
	elsif countc=2214 then   --<<----
	   tempSH<='1';               --SH給出低電平
	elsif countc=2215 then
	   tempLatch<='0';
           tempSH<='1';
	   countc<=0;
	end if;
     end if;   
     
     SH<=tempSH;
     Latch<=tempLatch;
     Efficiant<=tempEfficiant;
   end process;

   process(ccdin,askdata)
     begin
     if askdata='0' then
       if ccdin'event and ccdin='1' then
          jumpup<=countc;
       elsif ccdin'event and ccdin='0' then
          jumpdown<=countc;
       end if;
     end if;
   end process;

   process(dataclk,askdata)
     begin
     if askdata='1' then
	if dataclk'event and dataclk='1' then
            if addr0='0' and addr1='0' and addr2='0' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(0);
               data2<=conv_std_logic_vector(jumpdown,12)(0);
            elsif addr0='1' and addr1='0' and addr2='0' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(1);
               data2<=conv_std_logic_vector(jumpdown,12)(1);
            elsif addr0='0' and addr1='1' and addr2='0' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(2);
               data2<=conv_std_logic_vector(jumpdown,12)(2);
            elsif addr0='1' and addr1='1' and addr2='0' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(3);
               data2<=conv_std_logic_vector(jumpdown,12)(3);
            elsif addr0='0' and addr1='0' and addr2='1' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(4);
               data2<=conv_std_logic_vector(jumpdown,12)(4);
            elsif addr0='1' and addr1='0' and addr2='1' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(5);
               data2<=conv_std_logic_vector(jumpdown,12)(5);
            elsif addr0='0' and addr1='1' and addr2='1' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(6);
               data2<=conv_std_logic_vector(jumpdown,12)(6);
            elsif addr0='1' and addr1='1' and addr2='1' and addr3='0' then
  	       data1<=conv_std_logic_vector(jumpup,12)(7);
               data2<=conv_std_logic_vector(jumpdown,12)(7);
            elsif addr0='0' and addr1='0' and addr2='0' and addr3='1' then
  	       data1<=conv_std_logic_vector(jumpup,12)(8);
               data2<=conv_std_logic_vector(jumpdown,12)(8);
            elsif addr0='1' and addr1='0' and addr2='0' and addr3='1' then
  	       data1<=conv_std_logic_vector(jumpup,12)(9);
               data2<=conv_std_logic_vector(jumpdown,12)(9);
            elsif addr0='0' and addr1='1' and addr2='0' and addr3='1' then
  	       data1<=conv_std_logic_vector(jumpup,12)(10);
               data2<=conv_std_logic_vector(jumpdown,12)(10);
            elsif addr0='1' and addr1='1' and addr2='0' and addr3='1' then
  	       data1<=conv_std_logic_vector(jumpup,12)(11);
               data2<=conv_std_logic_vector(jumpdown,12)(11);
            else
  	       data1<='0';
               data2<='0';
            end if;
        end if; 
     end if;
   end process;

end behavioral;