#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file .\Ddoor.TCL
#-- Written on Sat Apr 19 17:35:51 2003


#-- begin a new section
project -new

#-- Device options
set_option -technology mach

#-- add_file options
add_file -vhdl -lib work "ddoor.vhd"

#-- top module name
set_option -top_module Ddoor

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#-- set result format/file last
project -result_file "Ddoor.edi"

#-- error message log file
project -log_file Ddoor.log

#-- let's save it
project -save Ddoor.tc_

#-- run Synplify
project -run

#-- **************************************************

#-- exit from Synplify
exit