?? top.syr
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Release 6.2i - xst G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.44 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.44 s | Elapsed : 0.00 / 1.00 s --> Reading design: top.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : top.prjInput Format : mixedIgnore Synthesis Constraint File : NOVerilog Include Directory : ---- Target ParametersOutput File Name : topOutput Format : NGCTarget Device : xc3s400-4-pq208---- Source OptionsTop Module Name : topAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesROM Style : AutoMux Extraction : YESMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESResource Sharing : YESMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESEquivalent register Removal : YESSlice Packing : YESPack IO Registers into IOBs : auto---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NOGlobal Optimization : AllClockNetsRTL Output : YesWrite Timing Constraints : NOHierarchy Separator : _Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : top.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESOptimize Instantiated Primitives : NO==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file E:/lqj/SRAM+FPGA+USB/дSRAM/USB-RAM/FPGA/top.vhdl in Library work.Entity <top> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <top> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - E:/lqj/SRAM+FPGA+USB/дSRAM/USB-RAM/FPGA/top.vhdl line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1304 - Contents of register <fifoaddr> in unit <top> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <OE_SRAM> in unit <top> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <CE_SRAM> in unit <top> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <UB_SRAM> in unit <top> never changes during circuit operation. The register is replaced by logic.Entity <top> analyzed. Unit <top> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is E:/lqj/SRAM+FPGA+USB/дSRAM/USB-RAM/FPGA/top.vhdl. Register <WE_SRAM> equivalent to <LB_SRAM> has been removed Register <sloe> equivalent to <slrd> has been removed Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 6 | | Transitions | 7 | | Inputs | 1 | | Outputs | 6 | | Clock | clk_SRAM (rising_edge) | | Clock enable | is_end (negative) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 000001 | | Power Up State | 000001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <slrd>. Found 16-bit register for signal <addr_SRAM>. Found 8-bit register for signal <data_SRAM>. Found 1-bit register for signal <LB_SRAM>. Found 1-bit register for signal <led>. Found 16-bit adder for signal <$n0017> created at line 105. Found 11-bit up counter for signal <count>. Found 8-bit register for signal <data_in>. Found 1-bit register for signal <is_end>. Found 16-bit register for signal <temp_addr_SRAM>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 52 D-type flip-flop(s). inferred 1 Adder/Subtracter(s).Unit <top> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Adders/Subtractors : 1 16-bit adder : 1# Counters : 1 11-bit up counter : 1# Registers : 14 1-bit register : 10 16-bit register : 2 8-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <top> ...Loading device for application Xst from file '3s400.nph' in environment D:/install/Xilinx.Mapping all equations...Building and optimizing final netlist ...?? 快捷鍵說明
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