Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 1.FlipFlop state_FFd1 has been replicated 1 time(s)FlipFlop state_FFd3 has been replicated 1 time(s)FlipFlop state_FFd1 has been replicated 1 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : top.ngrTop Level Output File Name         : topOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 45Macro Statistics :# Registers                        : 9#      1-bit register              : 4#      11-bit register             : 1#      16-bit register             : 2#      8-bit register              : 2# Adders/Subtractors               : 2#      11-bit adder                : 1#      16-bit adder                : 1Cell Usage :# BELS                             : 151#      GND                         : 1#      LUT1                        : 12#      LUT1_L                      : 16#      LUT2                        : 3#      LUT2_L                      : 1#      LUT3                        : 2#      LUT3_D                      : 2#      LUT3_L                      : 3#      LUT4                        : 7#      LUT4_D                      : 1#      LUT4_L                      : 52#      MUXCY                       : 25#      VCC                         : 1#      XORCY                       : 25# FlipFlops/Latches                : 72#      FD                          : 11#      FDE                         : 51#      FDRE                        : 9#      FDSE                        : 1# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 44#      IBUF                        : 10#      OBUF                        : 34=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4  Number of Slices:                      55  out of   3584     1%   Number of Slice Flip Flops:            72  out of   7168     1%   Number of 4 input LUTs:                99  out of   7168     1%   Number of bonded IOBs:                 44  out of    141    31%   Number of GCLKs:                        1  out of      8    12%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+count_10:Q                         | NONE                   | 61    |clk                                | BUFGP                  | 11    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 2.360ns (Maximum Frequency: 423.729MHz)   Minimum input arrival time before clock: 2.821ns   Maximum output required time after clock: 6.157ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'count_10:Q'Delay:               2.360ns (Levels of Logic = 3)  Source:            state_FFd4 (FF)  Destination:       data_SRAM_7 (FF)  Source Clock:      count_10:Q rising  Destination Clock: count_10:Q rising  Data Path: state_FFd4 to data_SRAM_7                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDRE:C->Q            13   0.000   0.895  state_FFd4 (state_FFd4)     LUT3_D:I1->O          4   0.000   0.629  Ker29111 (N2913)     LUT3_D:I0->O         11   0.000   0.836  Ker28381_1 (Ker28381_1)     LUT4_L:I3->LO         1   0.000   0.000  _n0016<6>1 (_n0016<6>)     FDE:D                     0.000          data_SRAM_6    ----------------------------------------    Total                      2.360ns (-0.000ns logic, 2.360ns route)                                       (-0.0% logic, 100.0% route)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay:               1.351ns (Levels of Logic = 2)  Source:            count_10 (FF)  Destination:       count_10 (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: count_10 to count_10                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q              62   0.000   1.351  count_10 (count_10)     LUT1:I0->O            0   0.000   0.000  count<10>_rt (count<10>_rt)     XORCY:LI->O           1   0.000   0.000  count_Madd__n0000_inst_sum_26 (count__n0000<10>)     FD:D                      0.000          count_10    ----------------------------------------    Total                      1.351ns (0.000ns logic, 1.351ns route)                                       (0.0% logic, 100.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'count_10:Q'Offset:              2.821ns (Levels of Logic = 2)  Source:            reset (PAD)  Destination:       data_in_7 (FF)  Destination Clock: count_10:Q rising  Data Path: reset to data_in_7                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O            12   0.641   0.865  reset_IBUF (reset_IBUF)     LUT2:I0->O           26   0.000   1.315  data_SRAM_N1171 (data_SRAM_N117)     FDE:CE                    0.000          data_SRAM_0    ----------------------------------------    Total                      2.821ns (0.641ns logic, 2.180ns route)                                       (22.7% logic, 77.3% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'count_10:Q'Offset:              6.157ns (Levels of Logic = 1)  Source:            slrd (FF)  Destination:       sloe (PAD)  Source Clock:      count_10:Q rising  Data Path: slrd to sloe                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDE:C->Q              3   0.000   0.577  slrd (sloe_OBUF)     OBUF:I->O                 5.580          slrd_OBUF (slrd)    ----------------------------------------    Total                      6.157ns (5.580ns logic, 0.577ns route)                                       (90.6% logic, 9.4% route)=========================================================================CPU : 6.11 / 6.98 s | Elapsed : 6.00 / 7.00 s --> Total memory usage is 71292 kilobytes