?? altera_mf.v
字號:
// ------------------------
// SUPPLY WIRE DECLARATION
// ------------------------
supply0 [int_width_a + int_width_b - 1 : 0] temp_mult_zero;
// ----------------
// WIRE DECLARATION
// ----------------
// Wire for Clock signals
wire input_a_wire_clk;
wire input_b_wire_clk;
wire addsub_wire_clk;
wire addsub_pipe_wire_clk;
wire zero_wire_clk;
wire zero_pipe_wire_clk;
wire sign_a_wire_clk;
wire sign_pipe_a_wire_clk;
wire sign_b_wire_clk;
wire sign_pipe_b_wire_clk;
wire multiplier_wire_clk;
wire mult_pipe_wire_clk;
wire output_wire_clk;
wire [width_a -1 : 0] scanouta;
wire [int_width_a + int_width_b -1 : 0] mult_out_latent;
wire [width_b -1 : 0] scanoutb;
wire addsub_int;
wire sign_a_int;
wire sign_b_int;
wire zero_acc_int;
wire sign_a_reg_int;
wire sign_b_reg_int;
wire addsub_latent;
wire zeroacc_latent;
wire signa_latent;
wire signb_latent;
wire mult_signed_latent;
wire [width_upper_data - 1 : 0] sload_upper_data_latent;
reg [int_width_result - 1 : 0] sload_upper_data_pipe_wire;
wire [int_width_a -1 :0] mult_a_wire;
wire [int_width_b -1 :0] mult_b_wire;
wire [width_upper_data - 1 : 0] sload_upper_data_wire;
wire [int_width_a -1 : 0] mult_a_tmp;
wire [int_width_b -1 : 0] mult_b_tmp;
wire zero_acc_wire;
wire zero_acc_pipe_wire;
wire sign_a_wire;
wire sign_a_pipe_wire;
wire sign_b_wire;
wire sign_b_pipe_wire;
wire addsub_wire;
wire addsub_pipe_wire;
wire mult_round_int;
wire mult_round_wire_clk;
wire mult_saturation_int;
wire mult_saturation_wire_clk;
wire accum_round_tmp1_wire;
wire accum_round_wire_clk;
wire accum_round_int;
wire accum_round_pipe_wire_clk;
wire accum_saturation_tmp1_wire;
wire accum_saturation_wire_clk;
wire accum_saturation_int;
wire accum_saturation_pipe_wire_clk;
wire accum_sload_upper_data_wire_clk;
wire accum_sload_upper_data_pipe_wire_clk;
wire [width_result -1 : width_result - width_upper_data] accum_sload_upper_data_int;
tri0 mult_is_saturated_wire;
// ------------------------
// COMPONENT INSTANTIATIONS
// ------------------------
ALTERA_DEVICE_FAMILIES dev ();
// --------------------
// ASSIGNMENT STATEMENTS
// --------------------
assign addsub_int = ((addnsub ===1'bz) ||
(addsub_wire_clk ===1'bz) ||
(addsub_pipe_wire_clk===1'bz)) ?
((accum_direction == "ADD") ? 1: 0) : addsub_pipe_wire;
assign sign_a_int = ((signa ===1'bz) ||
(sign_a_wire_clk ===1'bz) ||
(sign_pipe_a_wire_clk ===1'bz)) ?
((representation_a == "SIGNED") ? 1 : 0) : sign_a_pipe_wire;
assign sign_b_int = ((signb ===1'bz) ||
(sign_b_wire_clk ===1'bz) ||
(sign_pipe_b_wire_clk ===1'bz)) ?
((representation_b == "SIGNED") ? 1 : 0) : sign_b_pipe_wire;
assign sign_a_reg_int = ((signa ===1'bz) ||
(sign_a_wire_clk ===1'bz) ||
(sign_pipe_a_wire_clk ===1'bz)) ?
((representation_a == "SIGNED") ? 1 : 0) : sign_a_wire;
assign sign_b_reg_int = ((signb ===1'bz) ||
(sign_b_wire_clk ===1'bz) ||
(sign_pipe_b_wire_clk ===1'bz)) ?
((representation_b == "SIGNED") ? 1 : 0) : sign_b_wire;
assign zero_acc_int = ((accum_sload ===1'bz) ||
(zero_wire_clk===1'bz) ||
(zero_pipe_wire_clk===1'bz)) ?
0 : zero_acc_pipe_wire;
assign accum_sload_upper_data_int = ((accum_sload_upper_data === {width_upper_data{1'bz}}) ||
(accum_sload_upper_data_wire_clk === 1'bz) ||
(accum_sload_upper_data_pipe_wire_clk === 1'bz)) ?
{width_upper_data{1'b0}} : accum_sload_upper_data;
assign scanouta = mult_a_wire[int_width_a - 1 : int_width_a - width_a];
assign scanoutb = mult_b_wire[int_width_b - 1 : int_width_b - width_b];
assign {addsub_latent, zeroacc_latent, signa_latent, signb_latent, mult_signed_latent, mult_out_latent, sload_upper_data_latent, mult_is_saturated_latent} = (extra_multiplier_latency > 0) ?
mult_full : {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow};
assign mult_is_saturated = (port_mult_is_saturated != "UNUSED") ? mult_is_saturated_int : 0;
assign accum_is_saturated = (port_accum_is_saturated != "UNUSED") ? accum_is_saturated_latent : 0;
// ---------------------------------------------------------------------------------
// Initialization block where all the internal signals and registers are initialized
// ---------------------------------------------------------------------------------
initial
begin
// Checking for invalid parameters, in case Wizard is bypassed (hand-modified).
if ((dedicated_multiplier_circuitry != "AUTO") &&
(dedicated_multiplier_circuitry != "YES") &&
(dedicated_multiplier_circuitry != "NO"))
begin
$display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value.");
$stop;
end
if (width_a <= 0)
begin
$display("Error: width_a must be greater than 0.");
$stop;
end
if (width_b <= 0)
begin
$display("Error: width_b must be greater than 0.");
$stop;
end
if (width_result <= 0)
begin
$display("Error: width_result must be greater than 0.");
$stop;
end
if (( (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) &&
(dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) )
&& (input_source_a != "DATAA"))
begin
$display("Error: The input source for port A are limited to input dataa.");
$stop;
end
if (( (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) &&
(dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) )
&& (input_source_b != "DATAB"))
begin
$display("Error: The input source for port B are limited to input datab.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_rounding != "NO"))
begin
$display("Error: There is no rounding feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_rounding != "NO"))
begin
$display("Error: There is no rounding feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_saturation != "NO"))
begin
$display("Error: There is no saturation feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_saturation != "NO"))
begin
$display("Error: There is no saturation feature for non-StratixII device.");
$stop;
end
temp_sum = 0;
head_result = 0;
head_mult = 0;
overflow_int = 0;
mult_a_reg = 0;
mult_b_reg = 0;
zero_acc_reg = 0;
zero_acc_pipe_reg = 0;
sload_upper_data_reg = 0;
lower_bits = 0;
sload_upper_data_pipe_reg = 0;
sign_a_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
sign_a_pipe_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
sign_b_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
sign_b_pipe_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
addsub_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
addsub_pipe_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
result_int = 0;
result = 0;
overflow = 0;
mult_full = 0;
mult_res_out = 0;
mult_signed_out = 0;
mult_res = 0;
mult_is_saturated_int = 0;
mult_is_saturated_reg = 0;
mult_saturation_tmp = 0;
mult_saturate_overflow = 0;
accum_result = 0;
accum_saturate_overflow = 0;
accum_is_saturated_latent = 0;
for (i=0; i<=extra_accumulator_latency; i=i+1)
begin
result_pipe [i] = 0;
accum_saturate_pipe[i] = 0;
mult_is_saturated_pipe[i] = 0;
end
for (i=0; i<= extra_multiplier_latency; i=i+1)
begin
mult_pipe [i] = 0;
end
end
// ---------------------------------------------------------
// This block updates the internal clock signals accordingly
// every time the global clock signal changes state
// ---------------------------------------------------------
assign input_a_wire_clk = (input_reg_a == "UNREGISTERED")? 0:
(input_reg_a == "CLOCK0")? clock0:
(input_reg_a == "CLOCK1")? clock1:
(input_reg_a == "CLOCK2")? clock2:
(input_reg_a == "CLOCK3")? clock3:0;
assign input_b_wire_clk = (input_reg_b == "UNREGISTERED")? 0:
(input_reg_b == "CLOCK0")? clock0:
(input_reg_b == "CLOCK1")? clock1:
(input_reg_b == "CLOCK2")? clock2:
(input_reg_b == "CLOCK3")? clock3:0;
assign addsub_wire_clk = (addnsub_reg == "UNREGISTERED")? 0:
(addnsub_reg == "CLOCK0")? clock0:
(addnsub_reg == "CLOCK1")? clock1:
(addnsub_reg == "CLOCK2")? clock2:
(addnsub_reg == "CLOCK3")? clock3:0;
assign addsub_pipe_wire_clk = (addnsub_pipeline_reg == "UNREGISTERED")? 0:
(addnsub_pipeline_reg == "CLOCK0")? clock0:
(addnsub_pipeline_reg == "CLOCK1")? clock1:
(addnsub_pipeline_reg == "CLOCK2")? clock2:
(addnsub_pipeline_reg == "CLOCK3")? clock3:0;
assign zero_wire_clk = (accum_sload_reg == "UNREGISTERED")? 0:
(accum_sload_reg == "CLOCK0")? clock0:
(accum_sload_reg == "CLOCK1")? clock1:
(accum_sload_reg == "CLOCK2")? clock2:
(accum_sload_reg == "CLOCK3")? clock3:0;
assign accum_sload_upper_data_wire_clk = (accum_sload_upper_data_reg == "UNREGISTERED")? 0:
(accum_sload_upper_data_reg == "CLOCK0")? clock0:
(accum_sload_upper_data_reg == "CLOCK1")? clock1:
(accum_sload_upper_data_reg == "CLOCK2")? clock2:
(accum_sload_upper_data_reg == "CLOCK3")? clock3:0;
assign zero_pipe_wire_clk = (accum_sload_pipeline_reg == "UNREGISTERED")? 0:
(accum_sload_pipeline_reg == "CLOCK0")? clock0:
(accum_sload_pipeline_reg == "CLOCK1")? clock1:
(accum_sload_pipeline_reg == "CLOCK2")? clock2:
(accum_sload_pipeline_reg == "CLOCK3")? clock3:0;
assign accum_sload_upper_data_pipe_wire_clk = (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 0:
(accum_sload_upper_data_pipeline_reg == "CLOCK0")? clock0:
(accum_sload_upper_data_pipeline_reg == "CLOCK1")? clock1:
(accum_sload_upper_data_pipeline_reg == "CLOCK2")? clock2:
(accum_sload_upper_data_pipeline_reg == "CLOCK3")? clock3:0;
assign sign_a_wire_clk = (sign_reg_a == "UNREGISTERED")? 0:
(sign_reg_a == "CLOCK0")? clock0:
(sign_reg_a == "CLOCK1")? clock1:
(sign_reg_a == "CLOCK2")? clock2:
(sign_reg_a == "CLOCK3")? clock3:0;
assign sign_b_wire_clk = (sign_reg_b == "UNREGISTERED")? 0:
(sign_reg_b == "CLOCK0")? clock0:
(sign_reg_b == "CLOCK1")? clock1:
(sign_reg_b == "CLOCK2")? clock2:
(sign_reg_b == "CLOCK3")? clock3:0;
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