?? altera_mf.v
字號(hào):
assign sign_pipe_a_wire_clk = (sign_pipeline_reg_a == "UNREGISTERED")? 0:
(sign_pipeline_reg_a == "CLOCK0")? clock0:
(sign_pipeline_reg_a == "CLOCK1")? clock1:
(sign_pipeline_reg_a == "CLOCK2")? clock2:
(sign_pipeline_reg_a == "CLOCK3")? clock3:0;
assign sign_pipe_b_wire_clk = (sign_pipeline_reg_b == "UNREGISTERED")? 0:
(sign_pipeline_reg_b == "CLOCK0")? clock0:
(sign_pipeline_reg_b == "CLOCK1")? clock1:
(sign_pipeline_reg_b == "CLOCK2")? clock2:
(sign_pipeline_reg_b == "CLOCK3")? clock3:0;
assign multiplier_wire_clk = (multiplier_reg == "UNREGISTERED")? 0:
(multiplier_reg == "CLOCK0")? clock0:
(multiplier_reg == "CLOCK1")? clock1:
(multiplier_reg == "CLOCK2")? clock2:
(multiplier_reg == "CLOCK3")? clock3:0;
assign output_wire_clk = (output_reg == "UNREGISTERED")? 0:
(output_reg == "CLOCK0")? clock0:
(output_reg == "CLOCK1")? clock1:
(output_reg == "CLOCK2")? clock2:
(output_reg == "CLOCK3")? clock3:0;
assign mult_pipe_wire_clk = (multiplier_reg == "UNREGISTERED")? clock0:
multiplier_wire_clk;
assign mult_round_wire_clk = (mult_round_reg == "UNREGISTERED")? 0:
(mult_round_reg == "CLOCK0")? clock0:
(mult_round_reg == "CLOCK1")? clock1:
(mult_round_reg == "CLOCK2")? clock2:
(mult_round_reg == "CLOCK3")? clock3:0;
assign mult_saturation_wire_clk = (mult_saturation_reg == "UNREGISTERED")? 0:
(mult_saturation_reg == "CLOCK0")? clock0:
(mult_saturation_reg == "CLOCK1")? clock1:
(mult_saturation_reg == "CLOCK2")? clock2:
(mult_saturation_reg == "CLOCK3")? clock3:0;
assign accum_round_wire_clk = (accum_round_reg == "UNREGISTERED")? 0:
(accum_round_reg == "CLOCK0")? clock0:
(accum_round_reg == "CLOCK1")? clock1:
(accum_round_reg == "CLOCK2")? clock2:
(accum_round_reg == "CLOCK3")? clock3:0;
assign accum_round_pipe_wire_clk = (accum_round_pipeline_reg == "UNREGISTERED")? 0:
(accum_round_pipeline_reg == "CLOCK0")? clock0:
(accum_round_pipeline_reg == "CLOCK1")? clock1:
(accum_round_pipeline_reg == "CLOCK3")? clock3:0;
assign accum_saturation_wire_clk = (accum_saturation_reg == "UNREGISTERED")? 0:
(accum_saturation_reg == "CLOCK0")? clock0:
(accum_saturation_reg == "CLOCK1")? clock1:
(accum_saturation_reg == "CLOCK2")? clock2:
(accum_saturation_reg == "CLOCK3")? clock3:0;
assign accum_saturation_pipe_wire_clk = (accum_saturation_pipeline_reg == "UNREGISTERED")? 0:
(accum_saturation_pipeline_reg == "CLOCK0")? clock0:
(accum_saturation_pipeline_reg == "CLOCK1")? clock1:
(accum_saturation_pipeline_reg == "CLOCK2")? clock2:
(accum_saturation_pipeline_reg == "CLOCK3")? clock3:0;
// ----------------------------------------------------------------
// This block updates the internal clock enable signals accordingly
// every time the global clock enable signal changes state
// ----------------------------------------------------------------
assign input_a_wire_en = (input_reg_a == "UNREGISTERED")? 1:
(input_reg_a == "CLOCK0")? ena0:
(input_reg_a == "CLOCK1")? ena1:
(input_reg_a == "CLOCK2")? ena2:
(input_reg_a == "CLOCK3")? ena3:1;
assign input_b_wire_en = (input_reg_b == "UNREGISTERED")? 1:
(input_reg_b == "CLOCK0")? ena0:
(input_reg_b == "CLOCK1")? ena1:
(input_reg_b == "CLOCK2")? ena2:
(input_reg_b == "CLOCK3")? ena3:1;
assign addsub_wire_en = (addnsub_reg == "UNREGISTERED")? 1:
(addnsub_reg == "CLOCK0")? ena0:
(addnsub_reg == "CLOCK1")? ena1:
(addnsub_reg == "CLOCK2")? ena2:
(addnsub_reg == "CLOCK3")? ena3:1;
assign addsub_pipe_wire_en = (addnsub_pipeline_reg == "UNREGISTERED")? 1:
(addnsub_pipeline_reg == "CLOCK0")? ena0:
(addnsub_pipeline_reg == "CLOCK1")? ena1:
(addnsub_pipeline_reg == "CLOCK2")? ena2:
(addnsub_pipeline_reg == "CLOCK3")? ena3:1;
assign zero_wire_en = (accum_sload_reg == "UNREGISTERED")? 1:
(accum_sload_reg == "CLOCK0")? ena0:
(accum_sload_reg == "CLOCK1")? ena1:
(accum_sload_reg == "CLOCK2")? ena2:
(accum_sload_reg == "CLOCK3")? ena3:1;
assign accum_sload_upper_data_wire_en = (accum_sload_upper_data_reg == "UNREGISTERED")? 1:
(accum_sload_upper_data_reg == "CLOCK0")? ena0:
(accum_sload_upper_data_reg == "CLOCK1")? ena1:
(accum_sload_upper_data_reg == "CLOCK2")? ena2:
(accum_sload_upper_data_reg == "CLOCK3")? ena3:1;
assign zero_pipe_wire_en = (accum_sload_pipeline_reg == "UNREGISTERED")? 1:
(accum_sload_pipeline_reg == "CLOCK0")? ena0:
(accum_sload_pipeline_reg == "CLOCK1")? ena1:
(accum_sload_pipeline_reg == "CLOCK2")? ena2:
(accum_sload_pipeline_reg == "CLOCK3")? ena3:1;
assign accum_sload_upper_data_pipe_wire_en = (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 1:
(accum_sload_upper_data_pipeline_reg == "CLOCK0")? ena0:
(accum_sload_upper_data_pipeline_reg == "CLOCK1")? ena1:
(accum_sload_upper_data_pipeline_reg == "CLOCK2")? ena2:
(accum_sload_upper_data_pipeline_reg == "CLOCK3")? ena3:1;
assign sign_a_wire_en = (sign_reg_a == "UNREGISTERED")? 1:
(sign_reg_a == "CLOCK0")? ena0:
(sign_reg_a == "CLOCK1")? ena1:
(sign_reg_a == "CLOCK2")? ena2:
(sign_reg_a == "CLOCK3")? ena3:1;
assign sign_b_wire_en = (sign_reg_b == "UNREGISTERED")? 1:
(sign_reg_b == "CLOCK0")? ena0:
(sign_reg_b == "CLOCK1")? ena1:
(sign_reg_b == "CLOCK2")? ena2:
(sign_reg_b == "CLOCK3")? ena3:1;
assign sign_pipe_a_wire_en = (sign_pipeline_reg_a == "UNREGISTERED")? 1:
(sign_pipeline_reg_a == "CLOCK0")? ena0:
(sign_pipeline_reg_a == "CLOCK1")? ena1:
(sign_pipeline_reg_a == "CLOCK2")? ena2:
(sign_pipeline_reg_a == "CLOCK3")? ena3:1;
assign sign_pipe_b_wire_en = (sign_pipeline_reg_b == "UNREGISTERED")? 1:
(sign_pipeline_reg_b == "CLOCK0")? ena0:
(sign_pipeline_reg_b == "CLOCK1")? ena1:
(sign_pipeline_reg_b == "CLOCK2")? ena2:
(sign_pipeline_reg_b == "CLOCK3")? ena3:1;
assign multiplier_wire_en = (multiplier_reg == "UNREGISTERED")? 1:
(multiplier_reg == "CLOCK0")? ena0:
(multiplier_reg == "CLOCK1")? ena1:
(multiplier_reg == "CLOCK2")? ena2:
(multiplier_reg == "CLOCK3")? ena3:1;
assign output_wire_en = (output_reg == "UNREGISTERED")? 1:
(output_reg == "CLOCK0")? ena0:
(output_reg == "CLOCK1")? ena1:
(output_reg == "CLOCK2")? ena2:
(output_reg == "CLOCK3")? ena3:1;
assign mult_pipe_wire_en = (multiplier_reg == "UNREGISTERED")? ena0:
multiplier_wire_en;
assign mult_round_wire_en = (mult_round_reg == "UNREGISTERED")? 1:
(mult_round_reg == "CLOCK0")? ena0:
(mult_round_reg == "CLOCK1")? ena1:
(mult_round_reg == "CLOCK2")? ena2:
(mult_round_reg == "CLOCK3")? ena3:1;
assign mult_saturation_wire_en = (mult_saturation_reg == "UNREGISTERED")? 1:
(mult_saturation_reg == "CLOCK0")? ena0:
(mult_saturation_reg == "CLOCK1")? ena1:
(mult_saturation_reg == "CLOCK2")? ena2:
(mult_saturation_reg == "CLOCK3")? ena3:1;
assign accum_round_wire_en = (accum_round_reg == "UNREGISTERED")? 1:
(accum_round_reg == "CLOCK0")? ena0:
(accum_round_reg == "CLOCK1")? ena1:
(accum_round_reg == "CLOCK2")? ena2:
(accum_round_reg == "CLOCK3")? ena3:1;
assign accum_round_pipe_wire_en = (accum_round_pipeline_reg == "UNREGISTERED")? 1:
(accum_round_pipeline_reg == "CLOCK0")? ena0:
(accum_round_pipeline_reg == "CLOCK1")? ena1:
(accum_round_pipeline_reg == "CLOCK2")? ena2:
(accum_round_pipeline_reg == "CLOCK3")? ena3:1;
assign accum_saturation_wire_en = (accum_saturation_reg == "UNREGISTERED")? 1:
(accum_saturation_reg == "CLOCK0")? ena0:
(accum_saturation_reg == "CLOCK1")? ena1:
(accum_saturation_reg == "CLOCK2")? ena2:
(accum_saturation_reg == "CLOCK3")? ena3:1;
assign accum_saturation_pipe_wire_en = (accum_saturation_pipeline_reg == "UNREGISTERED")? 1:
(accum_saturation_pipeline_reg == "CLOCK0")? ena0:
(accum_saturation_pipeline_reg == "CLOCK1")? ena1:
(accum_saturation_pipeline_reg == "CLOCK2")? ena2:
(accum_saturation_pipeline_reg == "CLOCK3")? ena3:1;
// ---------------------------------------------------------
// This block updates the internal clear signals accordingly
// every time the global clear signal changes state
// ---------------------------------------------------------
assign input_a_wire_clr = (input_aclr_a == "UNREGISTERED")? 0:
(input_aclr_a == "ACLR0")? aclr0:
(input_aclr_a == "ACLR1")? aclr1:
(input_aclr_a == "ACLR2")? aclr2:
(input_aclr_a == "ACLR3")? aclr3:0;
assign input_b_wire_clr = (input_aclr_b == "UNREGISTERED")? 0:
(input_aclr_b == "ACLR0")? aclr0:
(input_aclr_b == "ACLR1")? aclr1:
(input_aclr_b == "ACLR2")? aclr2:
(input_aclr_b == "ACLR3")? aclr3:0;
assign addsub_wire_clr = (addnsub_aclr == "UNREGISTERED")? 0:
(addnsub_aclr == "ACLR0")? aclr0:
(addnsub_aclr == "ACLR1")? aclr1:
(addnsub_aclr == "ACLR2")? aclr2:
assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "UNREGISTERED")? 0:
(addnsub_pipeline_aclr == "ACLR0")? aclr0:
(addnsub_pipeline_aclr == "ACLR1")? aclr1:
(addnsub_pipeline_aclr == "ACLR2")? aclr2:
(addnsub_pipeline_aclr == "ACLR3")? aclr3:0;
assign zero_wire_clr = (accum_sload_aclr == "UNREGISTERED")? 0:
(accum_sload_aclr == "ACLR0")? aclr0:
(accum_sload_aclr == "ACLR1")? aclr1:
(accum_sload_aclr == "ACLR2")? aclr2:
(accum_sload_aclr == "ACLR3")? aclr3:0;
assign accum_sload_upper_data_wire_clr = (accum_sload_upper_data_aclr == "UNREGISTERED")? 0:
(accum_sload_upper_data_aclr == "ACLR0")? aclr0:
(accum_sload_upper_data_aclr == "ACLR1")? aclr1:
(accum_sload_upper_data_aclr == "ACLR2")? aclr2:
(accum_sload_upper_data_aclr == "ACLR3")? aclr3:0;
assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_pipeline_aclr == "ACLR3")? aclr3:0;
assign accum_sload_upper_data_pipe_wire_clr = (accum_sload_upper_data_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_upper_data_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_upper_data_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_upper_data_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_upper_data_pipeline_aclr == "ACLR3")? aclr3:0;
assign sign_a_wire_clr = (sign_aclr_a == "UNREGISTERED")? 0:
(sign_aclr_a == "ACLR0")? aclr0:
(sign_aclr_a == "ACLR1")? aclr1:
(sign_aclr_a == "ACLR2")? aclr2:
(sign_aclr_a == "ACLR3")? aclr3:0;
assign sign_b_wire_clr = (sign_aclr_b == "UNREGISTERED")? 0:
(sign_aclr_b == "ACLR0")? aclr0:
(sign_aclr_b == "ACLR1")? aclr1:
(sign_aclr_b == "ACLR2")? aclr2:
(sign_aclr_b == "ACLR3")? aclr3:0;
assign input_a_wire_clr = (input_aclr_a == "UNREGISTERED")? 0:
(input_aclr_a == "ACLR0")? aclr0:
(input_aclr_a == "ACLR1")? aclr1:
(input_aclr_a == "ACLR2")? aclr2:
(input_aclr_a == "ACLR3")? aclr3:0;
assign input_b_wire_clr = (input_aclr_b == "UNREGISTERED")? 0:
(input_aclr_b == "ACLR0")? aclr0:
(input_aclr_b == "ACLR1")? aclr1:
(input_aclr_b == "ACLR2")? aclr2:
(input_aclr_b == "ACLR3")? aclr3:0;
assign addsub_wire_clr = (addnsub_aclr == "UNREGISTERED")? 0:
(addnsub_aclr == "ACLR0")? aclr0:
(addnsub_aclr == "ACLR1")? aclr1:
(addnsub_aclr == "ACLR2")? aclr2:
(addnsub_aclr == "ACLR3")? aclr3:0;
assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "UNREGISTERED")? 0:
(addnsub_pipeline_aclr == "ACLR0")? aclr0:
(addnsub_pipeline_aclr == "ACLR1")? aclr1:
(addnsub_pipeline_aclr == "ACLR2")? aclr2:
(addnsub_pipeline_aclr == "ACLR3")? aclr3:0;
assign zero_wire_clr = (accum_sload_aclr == "UNREGISTERED")? 0:
(accum_sload_aclr == "ACLR0")? aclr0:
(accum_sload_aclr == "ACLR1")? aclr1:
(accum_sload_aclr == "ACLR2")? aclr2:
(accum_sload_aclr == "ACLR3")? aclr3:0;
assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_pipeline_aclr == "ACLR3")? aclr3:0;
assign sign_a_wire_clr = (sign_aclr_a == "UNREGISTERED")? 0:
(sign_aclr_a == "ACLR0")? aclr0:
(sign_aclr_a == "ACLR1")? aclr1:
(sign_aclr_a == "ACLR2")? aclr2:
(sign_aclr_a == "ACLR3")? aclr3:0;
assign sign_b_wire_clr = (?? 快捷鍵說(shuō)明
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